LTC1746 LINER [Linear Technology], LTC1746 Datasheet - Page 13

• Manufacturer Part Number: LTC1746
• Description: Low Power,14-Bit, 25Msps ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC1746 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capaci-
tor during the sampling period 1/(2F
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100 or less for each input. The S/H
circuit is optimized for a 50 source impedance. If the
source impedance is less than 50 , a series resistor
should be added to increase this impedance to 50 . The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
ANALOG
INPUT
0.1 F
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
100
U
1:1
U
100
25
25
W
12pF
4.7 F
12pF
12pF
ENCODE
25
25
V
A
A
CM
IN
IN
+
–
); however,
U
LTC1746
1746 F03
Input Drive Circuits
Figure 3 shows the LTC1746 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed
100
transformer is the loss of low frequency response. Most
small RF transformers have poor performance at frequen-
cies below 1MHz.
Figure 4 demonstrates the use of operational amplifiers to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
The 25
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
frequencies higher than 50MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
SINGLE-ENDED
2.35V 1/2
RANGE
INPUT
for each ADC input. A disadvantage of using a
resistors and 12pF capacitors on the analog
Figure 4. Differential Drive with Op Amps
100
500
+
–
+
–
1/2 LT1810
1/2 LT1810
5V
500
CM
25
25
, setting the ADC input
12pF
LTC1746
25
25
12pF
4.7 F
12pF
V
A
A
CM
IN
IN
+
–
13
LTC1746
1746f
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