LTC1746 LINER [Linear Technology], LTC1746 Datasheet - Page 15

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LTC1746

Manufacturer Part Number
LTC1746
Description
Low Power,14-Bit, 25Msps ADC
Manufacturer
LINER [Linear Technology]
Datasheet

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APPLICATIO S I FOR ATIO
Input Range
The input range can be set based on the application. For
oversampled signal processing in which the input fre-
quency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while main-
taining excellent SFDR. For high input frequencies
(>10MHz), the 2V range will have the best SFDR perfor-
mance but the SNR will degrade by 3.5dB. See the Typical
Performance Characteristics section.
V
THRESHOLD
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
U
CLOCK
INPUT
= 2V
0.1 F
U
Figure 7. Transformer Driven ENC/ENC with Equivalent Encode Input Circuit
0.1 F
ANALOG INPUT
50
2V
ENC
ENC
W
1:4
LTC1746
1746 F08a
ENC
ENC
U
LTC1746
V
V
DD
DD
2V BIAS
2V BIAS
6k
6k
Driving the Encode Inputs
The noise performance of the LTC1746 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
5V
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
MC100LVELT22
D0
BIAS
3.3V
Q0
Q0
130
83
TO INTERNAL
ADC CIRCUITS
3.3V
1746 F07
130
83
ENC
ENC
LTC1746
LTC1746
1746 F08b
15
1746f

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