LTC1865 LINER [Linear Technology], LTC1865 Datasheet - Page 13

• Manufacturer Part Number: LTC1865
• Description: Ultra-Tiny, Differential, 16-Bit ADC with SPI Interface SPI Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
sion operation can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
output the sign (D15) of the result of the just completed
conversion. While a low logic level is maintained at SCK
pin and CS is subsequently pulled high (CS = HIGH) the
remaining 15 bits of the result (D14:D0) are discarded
and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
2-Wire Operation
The 2-wire operation modes, while reducing the number of
required control signals, should be used only if the LTC2452
low power sleep capability is not required. In addition the
option to abort serial data transfers is no longer available.
Hardwire CS to GND for 2-wire operation.
CS = LOW
SD0
CS = LOW
SCK
SCK
SD0
CONVERT
CONVERT
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
SLEEP
clk
clk
D
D
1
15
15
DATA OUTPUT
1
clk
2
clk
D
D
14
14
2
Figure 13 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2452 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the sign (D15) of the
conversion result. The user must use external timing in
order to determine the end of conversion and result avail-
ability. Subsequently 16 clock pulses are applied to SCK
in order to serially shift the 16-bit result. The 16th clock
falling edge triggers a new conversion cycle.
clk
3
D
D
clk
13
DATA OUTPUT
13
3
clk
D
4
D
clk
12
12
4
clk
D
14
D
2
clk
2
15
clk
D
D
15
1
1
clk
16
clk
D
D
0
0
16
clk
17
CONVERT
CONVERT
LTC2452
2452 F13
2452 F14
13
2452fc