LTC1909-8 LINER [Linear Technology], LTC1909-8 Datasheet - Page 29

• Manufacturer Part Number: LTC1909-8
• Description: Wide Operating Range,No RSENSE TM Step-Down DC/DC Controller with SMBus Programming
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Each data byte is acknowledged in turn for all three Write
Word protocols but is only latched into Register 0 or 1 in
Setup protocol. This prevents previously loaded settings
from accidentally being changed. The first or Data Low
byte is loaded into Register 0. The second or Data High
byte is loaded into Register 1. After issuing the final
acknowledgment bit, the SMBus interface returns to an
idle state and waits for the next start bit.
Read Word Protocol
The Read Word protocol starts off like Write Word proto-
col but after the command code acknowledgment, the
microprocessor issues a second start bit (called a re-
peated start). This is followed by the slave address but with
the R/W bit set high to indicate that data direction is now
from the LTC1909-8 to the microprocessor. The LTC1909-8
then acknowledges the slave address and clocks the
contents of Register 0 (Data Low byte) to the micropro-
cessor. The Data Low byte is acknowledged by the micro-
processor. On detecting the acknowledgment bit, the
LTC1909-8 clocks out the contents of Register 1 (Data
High byte). As defined in the SMBus specifications, the
microprocessor does not acknowledge the last data byte.
The LTC1909-8 enters an idle state to wait for the next start
bit after clocking out the Data High byte. The five most
significant bits (VID0-VID4) of the Data Low and High
bytes are the resistor divider settings previously loaded
using the Setup protocol. The next bit below the VID0-
VID4 bits is the status of the DCON signal. If this bit is low
(high), the DC/DC converters are switched on (off). The
two unused, least significant bits of the Data Low and Data
High bytes are clocked out as zeros to eliminate the need
to mask out these bits in software.
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Operating Sequence
A typical control sequence for the LTC1909-8 is as follows:
• On power up, the DCON bit is preset to a high state by
• Pull VRON low as a precaution. Take SEL high or low to
• Use the Setup protocol to load the appropriate divider
• Use the Read-Back protocol to verify the contents of
• Repeat the setup and read-back if the codes are incor-
• Send two On protocols in succession to clear the DCON
• Use the Read-Back protocol to verify that the DCON is
• Pull VRON high. Since DCON = 0, the CPUON pin enters
• To shut down the supply, send two Off protocols to set
the power-on reset (POR) circuit. The CPUON pin is
pulled low to shut down the DC/DC converter. PGTMR
and PGOOD pull low to indicate that the converters are
not in regulation.
select the divider setting; e.g., one that suits the existing
power source (battery or wall-pack) or intended CPU
speed.
settings in Registers 0 and 1 and enable the On/Off state
machine.
Registers 0 and 1.
rect (due to bus conflicts).
bit.
low. A high state will indicate that an On command code
was corrupted by bus conflicts.
a high impedance state, allowing the DC/DC converter
to soft-start. PGTMR stays low for 50 s. PGOOD stays
low until the regulator output rises above the –7.5%
regulation limit.
the DCON bit high or pull VRON low if immediate
shutdown is required.
LTC1909-8
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