LTC2446 LINER [Linear Technology], LTC2446 Datasheet - Page 10

• Manufacturer Part Number: LTC2446
• Description: 24-Bit High Speed 8-Channel ?? ADCs with Selectable Multiple Reference Inputs
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
within the – 0.3V to (V
operating range, a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
LTC2446/LTC2447
10
BUSY
SDO
Table 2. LTC2446/LTC2447 Output Data Format
Differential Input Voltage
V
V
0.5 • V
0.25 • V
0.25 • V
0
–1LSB
– 0.25 • V
– 0.25 • V
– 0.5 • V
V
*The differential input voltage V
SCK
SDI
CS
IN
IN
IN
* ≥ 0.5 • V
* < –0.5 • V
*
REF
REF
REF
REF
REF
. For differential input voltages greater than
Hi-Z
REF
REF
** – 1LSB
**
** – 1LSB
**
**
** – 1LSB
REF
U
REF
1
BIT 31
**
EOC
**
1
CC
Figure 3. SDI Speed/Resolution, Channel Selection, and Data Output Timing
U
2
IN
BIT 30
“0”
+ 0.3V) absolute maximum
0
from –FS = –0.5 • V
+
and IN
3
BIT 29
IN
SIG
EN
= IN
W
Bit 31
EOC
4
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
–
0
0
0
0
0
0
0
0
0
0
+
MSB
SGL
– IN
pins is maintained
–
5
. **The differential reference voltage V
ODD
Bit 30
DMY
0
0
0
0
0
0
0
0
0
0
U
6
GLBL
REF
Bit 29
7
SIG
1
1
1
1
1
0
0
0
0
0
to
A1
8
A0
Bit 28
MSB
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
SERIAL INTERFACE PINS
The LTC2446/LTC2447 transmit the conversion results
and receive the start of conversion command through a
synchronous 3- or 4-wire interface. During the conver-
sion and sleep states, this interface can be used to assess
the converter status and during the data output state it is
used to read the conversion result and program the
speed, resolution and input channel.
1
0
0
0
0
1
1
1
1
0
9
OSR3
Bit 27
10
OSR2
0
1
1
0
0
1
1
0
0
1
REF
11
OSR1
= REF
Bit 26
0
1
0
1
0
1
0
1
0
1
12
+
BIT 20 BIT 19
OSR0 TWOX
– REF
13
Bit 25
–
.
0
1
0
1
0
1
0
1
0
1
14
…
…
…
…
…
…
…
…
…
…
…
BIT 0
32
Bit 0
LSB
0
1
0
1
0
1
0
1
0
1
24467 F03
Hi-Z
24467fa