LTC2446 LINER [Linear Technology], LTC2446 Datasheet - Page 16

• Manufacturer Part Number: LTC2446
• Description: 24-Bit High Speed 8-Channel ?? ADCs with Selectable Multiple Reference Inputs
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2446/LTC2447
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge and the
32nd falling edge of SCK, see Figure 5. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. Thirteen serial input
data bits are required in order to properly program the
speed/resolution and input/reference channel. If the data
16
CONVERSION
(EXTERNAL)
BUSY
SDO
SCK
SDI
CS
SLEEP
U
1
DATA OUTPUT
U
DON'T CARE
USER SELECTABLE
5
Figure 5. External Serial Clock, Reduced Output Data Length
REFERENCES
0.1V TO V
W
ANALOG
CONVERSION
INPUTS
1µF
4.5V TO 5.5V
CC
Hi-Z
28
24
23
12
22
29
30
11
10
1
8
9
7
BIT 31
U
EOC
V
REFG
REFG
REF01
REF01
REF67
REF67
CH0
CH1
CH2
CH7
COM
CC
. .
.
. .
.
LTC2446
2
+
–
BIT 30
+
–
+
–
“0”
BUSY
SDO
GND
SCK
SDI
CS
F
3
O
BIT 29
DON'T CARE
SIG
37
2
1,4,5,6,31,32,33
34
38
35
36
DATA OUTPUT
output sequence is aborted prior to the 13th rising edge of
SCK, the new input data is ignored, and the previously
selected speed/resolution and channel are used for the
next conversion cycle. This is useful for systems not
requiring all 32 bits of output data, aborting an invalid
conversion cycle or synchronizing the start of a conver-
sion. If a new channel is being programmed, the rising
edge of CS must come after the 14th falling edge of SCK
in order to store the data input sequence.
4
BIT 28 BIT 27 BIT 26 BIT 25
MSB
4-WIRE
SPI INTERFACE
5
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
6
Hi-Z
CONVERSION
TEST EOC
DON'T CARE
SLEEP
24467 F05
24467fa