SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet - Page 14

• Manufacturer Part Number: SC16C2550B_07
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
SC16C2550B_4
Product data sheet
Fig 7. Internal Loop-back mode diagram
RXRDYA, RXRDYB
TXRDYA, TXRDYB
INTA, INTB
CSA, CSB
D0 to D7
A0 to A2
RESET
IOW
IOR
SC16C2550B
converts the serial data back into parallel data that is then made available at the user data
interface D0 through D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The modem
control interrupts are also operational.
INTERRUPT
REGISTER
CONTROL
CONTROL
DATA BUS
SELECT
LOGIC
LOGIC
LOGIC
AND
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
XTAL1
REGISTERS
REGISTERS
GENERATOR
CLOCK AND
BAUD RATE
TRANSMIT
RECEIVE
FIFO
FIFO
XTAL2
TRANSMIT
REGISTER
REGISTER
RECEIVE
CONTROL
SHIFT
SHIFT
MODEM
LOGIC
SC16C2550B
MCR[4] = 1
002aaa599
© NXP B.V. 2007. All rights reserved.
TXA, TXB
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
DSRA, DSRB
(OP1A, OP2B)
RIA, RIB
(OP2A, OP2B)
CDA, CDB
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