SC16C2550B_07 PHILIPS [NXP Semiconductors], SC16C2550B_07 Datasheet - Page 15

• Manufacturer Part Number: SC16C2550B_07
• Description: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
• Manufacturer: PHILIPS [NXP Semiconductors]

NXP Semiconductors
7. Register descriptions
Table 8.
[1]
[2]
[3]
SC16C2550B_4
Product data sheet
A2
General register set
0
0
0
0
0
0
1
1
1
1
Special register set
0
0
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
Accessible only when LCR[7] is logic 0.
Baud rate registers accessible only when LCR[7] is logic 1.
A1
0
0
0
1
1
1
0
0
1
1
0
0
A0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C2550B internal registers
Register Default
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
7.1 Transmit (THR) and Receive (RHR) Holding Registers
[3]
[2]
Table 8
assigned bit functions are more fully defined in
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 through D0)
to the TSR and UART via the THR, providing that the THR is empty. The THR empty flag
in the LSR register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550B and
receive FIFO by reading the RHR register. The receive section provides a mechanism to
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
details the assigned bit functions for the SC16C2550B internal registers. The
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
CD
bit 7
bit 7
bit 15
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set break set parity even
0
THR and
TSR
empty
RI
bit 6
bit 6
bit 14
Bit 5
bit 5
bit 5
0
reserved
0
0
0
THR
empty
DSR
bit 5
bit 5
bit 13
Bit 4
bit 4
bit 4
0
reserved
0
0
parity
loop
back
break
interrupt
CTS
bit 4
bit 4
bit 12
Section 7.1
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
OP2/INT
enable
framing
error
bit 3
bit 3
bit 11
CD
through
SC16C2550B
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
(OP1)
parity
error
bit 2
bit 2
bit 10
RI
Section
© NXP B.V. 2007. All rights reserved.
Bit 1
bit 1
bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
DSR
7.10.
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
CTS
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