AD7545AN Intersil Corporation, AD7545AN Datasheet - Page 4

• Manufacturer Part Number: AD7545AN
• Description: 12-Bit/ Buffered/ Multiplying CMOS DAC
• Manufacturer: Intersil Corporation

NOTES:
10. V
11. All input signal rise and fall times measured from 10% to 90% of
12. Timing measurement reference level is (V
13. Since input data latches are transparent for CS and WR both
Circuit Information - D/A Converter Section
Figure 2 shows a simplified circuit of the D/A converter
section of the AD7545. Note that the ladder termination
resistor is connected to AGND. R is typically 11k .
The binary weighted currents are switched between the OUT1
bus line and AGND by N-Channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state. One of the current switches is shown in Figure 3.
The capacitance at the OUT1 bus line, C
dependent and varies from 70pF (all switches to AGND) to
200pF (all switches to OUT1).
The input resistance at V
R
WRITE MODE:
CS and WR low, DAC responds
to data bus (DB0 - DB11) inputs
9. V
LDR
V
(MSB)
REF
DB11
V
low, it is preferred to have data valid before CS and WR both go
low. This prevents undesirable changes at the analog output
while the data inputs settle.
FIGURE 3. N-CHANNEL CURRENT STEERING SWITCH
DD
DD
DD
(R
FIGURE 2. SIMPLIFIED D/A CIRCUIT OF AD7545
2R
.
= +5V; t
= +15V; t
LDR
R
DB10
is the R/2R ladder characteristic resistance and is
INTERFACE
2R
r
R
= t
r
= t
LOGIC
DB9
FROM
f
= 20ns
f
MODE SELECTION
= 40ns
2R
R
REF
DB1
AGND
(Figure 2) is always equal to
HOLD MODE:
Either CS or WR high, data bus
(DB0 - DB11) is locked out; DAC
holds last data present when
WR or CS assumed high state.
TO LADDER
2R
R
(LSB)
DB0
OUT1
2R
IH
+ V
2R
OUT1
IL
)/2.
, is code
R
OUT1
AGND
FB
AD7545
10-13
equal to the value “R”). Since R
the reference terminal can be driven by a reference voltage or a
reference current, AC or DC, of positive or negative polarity. (If a
current source is used, a low temperature coefficient external
R
Circuit Information - Digital Section
Figure 4 shows the digital structure for one bit. The digital
signals CONTROL and CONTROL are generated from CS
and WR.
The input buffers are simple CMOS inverters designed such
that when the AD7545 is operated with V
convert TTL input levels (2.4V and 0.8V) into CMOS logic
levels. When V
buffers operate in their linear region and draw current from
the power supply. To minimize power supply currents it is
recommended that the digital input voltages be as close to
the supply rails (V
The AD7545 may be operated with any supply voltage in the
range 5V
levels are CMOS compatible only, i.e., 1.5V and 13.5V.
Application
Output Offset
CMOS current-steering D/A converters exhibit a code
dependent output resistance which in turn causes a code
dependent amplifier noise gain. The effect is a code depen-
dent differential nonlinearity term at the amplifier output
which depends on V
offset voltage. To maintain monotonic operation it is recom-
mended that V
the temperature range of operation.
General Ground Management
AC or transient voltages between AGND and DGND can
cause noise injection into the analog output. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7545. In
more complex systems where the AGND and DGND con-
nection is on the backplane, it is recommended that two
diodes be connected in inverse parallel between the AD7545
AGND and DGND pins (1N914 or equivalent).
Digital Glitches
When WR and CS are both low the latched are transparent
and the D/A converter inputs follow the data inputs. In some
FB
INPUTS BUFFERS
is recommended to define scale factor).
FIGURE 4. DIGITAL INPUT STRUCTURE
V
DD
OS
IN
CONTROL
DD
be no greater than (25 x 10
is in the region of 2.0V to 3.5V the input
15V. With V
and DGND) as is practically possible.
OS
where V
CONTROL
IN
DD
at the V
OS
= +15V the input logic
is the amplifier input
DD
REF
TO AGND SWITCH
TO OUT1 SWITCH
= 5V, the buffers
-6
pin is constant,
) (V
REF
) over