CY7C1370C Cypress, CY7C1370C Datasheet - Page 20

• Manufacturer Part Number: CY7C1370C
• Description: 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: Cypress

Document #: 38-05233 Rev. *D
Switching Characteristics
Switching Waveforms
Notes:
23. For this waveform ZZ is tied low.
24. When CE is LOW, CE
25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Read/Write/Timing
AS
DS
CENS
WES
ALS
CES
AH
DH
CENH
WEH
ALH
CEH
Parameter
In-Out (DQ)
ADDRESS
ADV/LD
Data
BW
CEN
CLK
WE
OE
CE
x
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BW
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
t
t
t
CENS
CES
AS
WRITE
1
D(A1)
[23,24,25]
A1
is LOW, CE
1
t
t
CENH
t
AH
CEH
x
x
Set-up Before CLK Rise
Hold After CLK Rise
2
WRITE
D(A2)
is HIGH and CE
Description
2
A2
t
CH
Over the Operating Range
t CYC
t
t
DS
CL
D(A2+1)
BURST
WRITE
D(A1)
3
3
t
is LOW. When CE is HIGH,CE
DH
DON’T CARE
Q(A3)
D(A2)
READ
A3
4
[ 21, 22]
Min. Max. Min. Max. Min. Max. Min. Max.
D(A2+1)
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
Q(A4)
READ
A4
5
-250
t
t
CO
CLZ
1
(continued)
is HIGH or CE
UNDEFINED
Q(A4+1)
BURST
READ
Q(A3)
6
t
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
DOH
-225
t
OEHZ
2
is LOW or CE
WRITE
D(A5)
Q(A4)
A5
7
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
t
OEV
t
OELZ
3
-200
is HIGH.
Q(A4+1)
READ
Q(A6)
A6
8
t
t
DOH
CHZ
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
CY7C1370C
CY7C1372C
WRITE
D(A7)
D(A5)
-167
9
A7
Page 20 of 27
DESELECT
10
Q(A6)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns