CY7C1370C Cypress, CY7C1370C Datasheet - Page 21

• Manufacturer Part Number: CY7C1370C
• Description: 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: Cypress

Document #: 38-05233 Rev. *D
Switching Waveforms
Notes:
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28. I/Os are in High-Z when exiting ZZ sleep mode.
NOP,STALL AND DESELECT CYCLES
ZZ Mode Timing
In-Out (DQ)
ADDRESS
ADV/LD
Data
BWx
CEN
CLK
WE
CE
ALL INPUTS
(except ZZ)
Outputs (Q)
I
SUPPLY
WRITE
D(A1)
CLK
[27,28]
A1
1
ZZ
READ
Q(A2)
A2
(continued)
2
t ZZI
t ZZ
I DDZZ
STALL
3
[23,24,26]
D(A1)
Q(A3)
READ
A3
4
DON’T CARE
Q(A2)
WRITE
D(A4)
DON’T CARE
A4
5
High-Z
STALL
6
Q(A3)
UNDEFINED
NOP
DESELECT or READ Only
7
t RZZI
t ZZREC
D(A4)
READ
Q(A5)
A5
8
DESELECT
CY7C1370C
CY7C1372C
9
Page 21 of 27
CONTINUE
DESELECT
Q(A5)
10
t
CHZ