W83194R-KX Winbond, W83194R-KX Datasheet - Page 7

• Manufacturer Part Number: W83194R-KX
• Description: 133MHZ 3-DIMM K7 CLOCK
• Manufacturer: Winbond

8.0 FUNTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO to stabilize prior to enabling clock outputs to assure
correct pulse widths.
functions are not available. The W83194R-KXmay be disabled in the low state according to the PD#
pin41 in order to reduce power consumption. All clocks are stopped in the Power Down state when
PD# is set to LOW, but maintain a valid high period on transitions from running to stop.
8.2 2-WIRE I
The clock generator is a slave I
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled.
W83194R-KX initializes with default register settings. Use of the 2-wire control interface is then
optional.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a “Start” condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking.
reception of each byte, an “acknowledge“ (low) on the SDATA wire will be generated by the clock
chip. Controller can start to write to internal I
order is as follows:
Bytes sequence order for I
Set R/W to 1 when “Read back”, the data sequence is as follows, address is [1101 0011] :
Clock Address
A(6:0) & R/W
Clock Address
A(6:0) & R/W
2
C CONTROL INTERFACE
Ack
Ack
When MODE=0, pins 2 is inputs (CPU_STOP#), when MODE=1, these
2
C controller :
8 bits dummy
Command code
Byte 0
2
C component which can be read back the data stored in the latches
Ack
Ack
- 7 -
2
C registers after the string of data. The sequence
8 bits dummy
Byte count
Byte 1
Publication Release Date: Nov. 1999
Ack
Ack
W83194R-KX
Byte0,1,2...
until Stop
Byte2, 3, 4...
until Stop
PRELIMINARY
On power up, the
After successful
Revision 0.35