W83194R-630 WINBOND [Winbond], W83194R-630 Datasheet
W83194R-630
Related parts for W83194R-630
W83194R-630 Summary of contents
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... Register 5: SDRAM Register(1 = Active Inactive) ...................................................12 8.2.8 Register 6: Winbond Chip ID Register (Read Only)......................................................12 9. ORDERING INFORMATION .................................................................................................... 12 10. HOW TO READ THE TOP MARKING...................................................................................... 13 11. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 14 12. REVISION HISTORY ................................................................................................................ 15 W83194R-630/-630A Data Sheet 166MHZ CLOCK FOR SIS CHIPSET - 1 - Publication Release Date: May 13, 2005 Revision A1 ...
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... W83194R-630A provides the 0.5%, 0.75% center type and 0~0.5% down type spread spectrum to reduce EMI. The W83194R-630A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± ...
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... Xin Xout *FS(0:3) 4 *MODE SEL3.3_2.5# CPU_STOP# PCI_STOP# PD# *SDATA *SCLK PLL2 ÷2 XTAL OSC PLL1 STOP Spread Spectrum CPU_STOP# LATCH 5 PCI STOP clock POR Divder Control Logic PCI_STOP# Config. Reg W83194R-630/-630A 48MHz 24_48MHz REF(0:1) 2 CPUCLK(0:2 3 SDRAM(0:13 14 PCICLK(0:6) 7 Publication Release Date:May 13, 2005 Revision A1 ...
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... I/O Crystal input with internal loading capacitors and 4 IN feedback resistors. 5 OUT Crystal output at 14.318MHz nominally W83194R-630/-630A REF1 VddLCPU CPUCLK_F CPUCLK0 Vss CPUCLK1 VddSD SDRAM12 SDRAM_F Vss SDRAM11 SDRAM 10 VddSD SDRAM 9 SDRAM 8 Vss SDRAM 7 SDRAM 6 VddSD ...
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... CPU_STOP#, PCI_STOP# and PD#. When MODE=1, the above pins are SDRAM clock 9 I/O outputs. When MODE=0, the pins are inputs ACPI pins. PCI clock during normal operation. OUT Low skew (< 250ps) PCI clock outputs W83194R-630/-630A FUNCTION Publication Release Date:May 13, 2005 Revision A1 ...
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... PIN Power supply for REF crystal and core logic. Power supply for CPUCLK_F and CPUCLK[0:1], either 2.5V or 3.3V. Power supply for PCI outputs. Power supply for SDRAM and 48/24NHz outputs W83194R-630/-630A FUNCTION 2 C 2-wire control interface 2 C 2-wire control interface FUNCTION FUNCTION ...
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... W83194R-630/-630A REF (MHZ) PCI (MHZ) IOAPIC 33.4 14.318 33.4 14.318 33.2 14.318 33.4 14.318 37.5 14.318 33.4 14.318 33.4 14.318 33.4 14.318 33.4 14.318 32.3 14.318 32.3 14.318 31.7 14.318 35 14.318 37.3 14.318 32.1 14.318 33.3 14 ...
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... All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. W83194R-630A initializes with default register settings, and then itptional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer ...
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... W83194R-630/-630A CPU SDRAM SSEL0 (MHZ) (MHZ) 0 66.8 100.2 1 100.2 100.2 0 83.3 83.3 1 133.6 100 100.2 133.6 0 100.2 150.3 1 133.6 133.6 0 66.8 66 ...
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... SSEL3 (for frequency table selection by software via Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs - Latched FS2# - Reserved 0 = 0.5% down type spread, overrides Byte0-bit7 Center type spread. - Reserved 43 CPUCLK2 (Active / Inactive) 45 CPUCLK1 (Active / Inactive) 46 CPUCLK0 (Active / Inactive) - Reserved - 10 - W83194R-630/-630A DESCRIPTION Bit 2, 6 DESCRIPTION ...
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... Inactive) - Reserved - Reserved 48 REF1 (Active / Inactive) 2 REF0X2 (Active / Inactive) DESCRIPTION SDRAM13 (Active / Inactive) SDRAM12 (Active / Inactive) SDRAM11 (Active / Inactive) SDRAM10 (Active / Inactive) Latched FS1# SDRAM9 (Active / Inactive) Latched FS3# SDRAM8 (Active / Inactive W83194R-630/-630A DESCRIPTION Publication Release Date:May 13, 2005 Revision A1 ...
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... SDRAM4 (Active / Inactive) SDRAM3 (Active / Inactive) SDRAM2 (Active / Inactive) SDRAM1 (Active / Inactive) SDRAM0 (Active / Inactive) - Winbond Chip ID - Winbond Chip ID - Winbond Chip ID - Winbond Chip ID - Winbond Chip ID - Winbond Chip ID - Winbond Chip ID - Winbond Chip ID PACKAGE TYPE 48 PIN SSOP - 12 - W83194R-630/-630A DESCRIPTION PRODUCTION FLOW Commercial +70 C ...
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... HOW TO READ THE TOP MARKING W83194R-630A 28051234 942GED 1st line: Winbond logo and the type number: W83194R-630A 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 942: packages made in '99, week 42 G: assembly house ID ...
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... PACKAGE DRAWING AND DIMENSIONS W83194R-630/-630A - 14 - ...
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... FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 15 - W83194R-630/-630A DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...