W83194R-39A WINBOND [Winbond], W83194R-39A Datasheet

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W83194R-39A

Manufacturer Part Number
W83194R-39A
Description
100MHZ 3-DIMM CLOCK
Manufacturer
WINBOND [Winbond]
Datasheet
1.0 GENERAL DESCRIPTION
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of
CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by
the none-delay buffer_in pin.
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. Spread spectrum built in at ¡Ó 0.5% or ¡Ó 0.25% to reduce EMI. Programmable stopping
individual clock outputs and frequency selection through I
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after
power-up. It is not recommend to use the dual function pin for the slots(ISA, PCI, CPU, DIMM). The
add on cards may have a pull up or pull down.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50 ¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium
2 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 50 MHz to 133 MHz CPU
I
2
C 2-Wire serial interface and I
II CPU with I
2
2
C read back
C.
- 1 -
100MHZ 3-DIMM CLOCK
2
C interface.
Publication Release Date: May 1998
W83194R-39/-39A
The device meets the
Revision 0.20

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W83194R-39A Summary of contents

Page 1

... The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by the none-delay buffer_in pin ...

Page 2

... STOP Spread Spectrum 3 FS(0:2)* STOP LATCH MODE PCI STOP Clock POR Divider CPU_STOP# Control PCI_STOP# Logic SDATA* Config. Reg. SDCLK* W83194R-39/-39A W83194R-39A 48MHz PLL2 24MHz ~ Xin XTAL IOAPIC OSC Xout REF(0:1) BUFFER CPUCLK_F PLL1 CPUCLK1 Spread Spectrum 4 SDRAM(0:12) FS(0:3)* LATCH 13 MODE* ...

Page 3

... PIN CONFIGURATION Vddq1 PCI_STOP#/REF0 Vddq2 PCICLK_F/MODE* (W83194R-39A ) PCICLK0/FS3* PCICLK1 PCICLK2 PCICLK3 PCICLK4 Vddq2 BUFFER IN SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 SDATA SDCLK 5.0 PIN DESCRIPTION IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low * - Internal 250k pull- Vss Xin 4 Xout Vss ...

Page 4

... PIN Xin Xout 5.2 CPU, SDRAM, PCI, IOAPIC Clock Outputs SYMBOL PIN CPUCLK_F CPUCLK1 CPU_STOP# IOAPIC SDRAM [ 0:12] 17,18,20,21,28 ,29,31,32,34, 35,37,38,40 PCICLK_F/ *MODE PCICLK0/*FS3 (W83194R-39A) PCICLK [ 0:4 ] 8,10,11,12,13 (W83194R-39) BUFFER IN SDRAM [ 17,18,20,21, 28,29,31,32, 34,35,37,38 I Crystal input with internal loading capacitors and feedback resistors. 5 OUT Crystal output at 14.318MHz nominally. ...

Page 5

... Power supply for PCICLK_F, PCICLK[0:4], 3.3V. Power supply for SDRAM[0:12], and CPU PLL core, nominal 3.3V. 27 Power for 24 & 48MHz output buffers and fixed PLL core W83194R-39/-39A PRELIMINARY FUNCTION 2 C 2-wire control interface with internal 2 C 2-wire control interface with FUNCTION ...

Page 6

... FREQUENCY SELECTION 6.1 Frequency table of W83194R-39 FS2 FS1 FS0 6.2 Frequency table of W83194R-39A FS3=0 FS2 FS1 FS0 FS3=1 FS2 ...

Page 7

... MODE PIN -POWER MANAGEMENT INPUT CONTROL MODE, Pin7 (Latched Input W83194R-39/-39A PIN 2 PCI_STOP# (Input) REF0 (Output) Publication Release Date: May 1998 - 7 - PRELIMINARY Revision 0.20 ...

Page 8

... The W83194R-39/-39Amay be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop ...

Page 9

... Selection by software I SSEL3 (for frequency table selection by software via Normal 1 = Spread Spectrum enabled 0 = Running 1 = Tristate all outputs the same as the hardware setting - 9 - W83194R-39/-39A PRELIMINARY Byte0,1,2... Ack until Stop Byte2, 3, 4... Ack until Stop byte must be sent following the ...

Page 10

... Outputs PCI SDRAM Hi-Z Hi-Z see table CPU Description Latched FS2# Reserved Reserved Reserved SDRAM12 (Active / Inactive) Reserved CPUCLK1 (Active / Inactive) CPUCLK_F (Active / Inactive W83194R-39/-39A PRELIMINARY REF IOAPIC Hi-Z Hi-Z 14.318 14.318 Publication Release Date: May 1998 Revision 0.20 ...

Page 11

... PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLk1 (Active / Inactive) PCICLK0 (Active / Inactive) - Reserved - Reserved 48MHz (Active / Inactive) 24MHz (Active / Inactive) - Reserved SDRAM(8:11) (Active / Inactive) SDRAM(4:7) (Active / Inactive) SDRAM(0:3) (Active / Inactive W83194R-39/-39A PRELIMINARY Description Description Publication Release Date: May 1998 Revision 0.20 ...

Page 12

... Latched Frequency Selects(FS#) will be inverted logic load of the input frequency select pin conditions. Description Reserved Reserved Reserved Reserved Latched FS1# Reserved Reserved Reserved Description Reserved Reserved Reserved IOAPIC (Active / Inactive) Reserved Reserved REF1 (Active / Inactive) REF0 (Active / Inactive W83194R-39/-39A PRELIMINARY Publication Release Date: May 1998 Revision 0.20 ...

Page 13

... JA BW 500 J 0.4 1.6 t TLH t THL V 0.7 1.5 over V 0.7 2.1 RBE - 13 - W83194R-39/-39A PRELIMINARY Rating - 0 7 150 125 + Units Test Conditions % Measured at 1. Load Measured at 1. Load Measured at 1. KHz Load on CPU and PCI ...

Page 14

... 0 2 Ioz 10 I dd3 I dd2 CPUS3 CPUS2 I PD3 - 14 - W83194R-39/-39A PRELIMINARY = + Units Test Conditions All outputs V dc All outputs using 3.3V power CPU = 66.6 MHz PCI = 33.3 Mhz with load mA Same as above ...

Page 15

... OH(min) -27 OH(max) I OL(min OL(max) 0.4 RF(min) 1.6 RF(max) Min Typ Max -29 OL(min) 28 OL(max) 0.4 RF(min) 1.8 RF(max W83194R-39/-39A PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 2.0V mA Vout = 1 Vout = 0 10pF Load ns 20pF Load Units Test Conditions mA Vout = 1 Vout = 2 Vout = 1 Vout = 0 ...

Page 16

... Typ Max -46 OL(min) 53 OL(max) 0.5 RF(min) 1.3 RF(max) Min Typ Max -33 -33 30 OL(min) 38 OL(max) 0.5 RF(min) 2.0 RF(max W83194R-39/-39A PRELIMINARY Units Test Conditions mA Vout = 1 Vout = 3.135V mA Vout = 1. Vout = 0 10pF Load ns 20pF Load Units Test Conditions mA Vout = 1. Vout = 3.135 V mA Vout = 1. Vout = 0 ...

Page 17

... In this case, PCI “c locks on latency “ is less than 2 PCI clocks and “c locks off latency ” is less then 2 PCI clocks W83194R-39/-39A PRELIMINARY Publication Release Date: May 1998 Revision 0.20 ...

Page 18

... These capacitor has typical values ranging from 4.7pF to 22pF. 2.5V Output pull-low Output tri-state Within 3ms Input Output Output pull-low Output tri-state @3.3V ) inside. The default state will be logic - 18 - W83194R-39/-39A PRELIMINARY Vdd resistor is recommended to be the series Publication Release Date: May 1998 Revision 0.20 ...

Page 19

... Terminating Resistor Device Pin 10k Ground Programming Header Vdd Pad Ground Pad Series 10k Terminating Resistor Device Pin - 19 - W83194R-39/-39A PRELIMINARY Clock Trace EMI Reducing Cap Optional Ground Clock Trace EMI Reducing Cap Optional Ground Publication Release Date: May 1998 ...

Page 20

... ORDERING INFORMATION Part Number W83194R-39/-39A 14.0 HOW TO READ THE TOP MARKING W83194R-39 28051234 814GBB W83194R-39A 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-39/-39A 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number ...

Page 21

... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. W83194R-39/-39A Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong ...

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