PCA84C646 Philips Semiconductors, PCA84C646 Datasheet - Page 10

• Manufacturer Part Number: PCA84C646
• Description: Microcontrollers for TV tuning control and OSD applications
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.2
The PCA84C646 and PCA84C846 have a PWM DAC
output (TDAC) with a resolution of 16384 levels for
Voltage Synthesized Tuning (VST).
Figure 6 shows the block diagram of the 14-bit PWM DAC
which consists of:
The contents of the interface latches VSTH and VSTL are
latched into VSTREG. The upper seven bits of VSTREG
are used for coarse adjustment, while the lower seven bits
are used for fine adjustment.
The contents of the interface latches VSTH and VSTL are
latched into VSTREG at the beginning of the first t
VSTL is written (see Fig.7). After VSTH and VSTL are
latched into VSTREG, it takes one t
appropriate pulse pattern.
Therefore, to ensure correct digital-to-analog conversion,
two t
next sequence (changing the contents of VSTH and
VSTL).
To ensure that the correct data is latched into VSTREG,
VSTH must contain the correct value before VSTL is
written; see the note in Fig.7.
The repetition times of the pulse controllers are:
Output TDAC shares the same pin as DP13; bit TDACE
(Derivative Register 22; see Table 22) selects the function
of pin DP13/TDAC.
Table 4 Selection of pin function DP13/TDAC
1995 Jun 15
Two 7-bit DAC interface latches (see Table 40):
– VSTH: Derivative Register 18; address 18H.
– VSTL: Derivative Register 19; address 19H.
One 14-bit DAC data latch: VSTREG, which contents
defines the HIGH-time.
14-bit counter.
Pulse control.
Coarse, upper seven bits (VSTH):
Fine, lower seven bits (VSTL):
Microcontrollers for TV tuning
control and OSD applications
t
t
sub
r
TDACE
sub
=
VST control 14-bit PWM DAC
128 t
=
1
0
periods should be allowed before beginning the
128 3 f
sub
=
xtal
49152 f
TDAC; 14-bit PWM output
xtal
FUNCTION
DP13
sub
to generate the
sub
after
10
7.2.1
An active HIGH pulse is generated in every subperiod; the
pulse width being determined by the contents of VSTH.
The coarse output (OUT1) is LOW at the start of each
subperiod and will remain LOW during
Where t
The output will then go HIGH and remain HIGH until the
start of the next subperiod. The coarse pulse width may be
calculated as:
7.2.2
Fine adjustment is achieved by generating an additional
pulse in specific subperiods. The pulse is added at the
start of the selected subperiod and has a pulse width of
3/f
subperiods a fine pulse will be added. It is the logic 0 state
of the value held in VSTL that actually selects the
subperiods. When more than one bit is a logic 0 then the
subperiods selected will be a combination of those
subperiods specified in Table 5. For example, if
VSTL = 111 1010 then this is a combination of:
Pulses will be added in subperiods 16, 48, 64, 80 and 112.
This example is illustrated in Fig.9.
When VSTL holds 111 1111 fine adjustment is inhibited
and the TDAC output is determined only by the contents of
VSTH.
Table 5 Additional pulse distribution
t
s
VSTL = 111 1110: subperiod 64 and
VSTL = 111 1011: subperiods 16, 48, 80 and 112.
xtal
111 1101
111 1011
101 1111
111 1110
111 0111
110 1111
011 1111
------------------------------------------ -
VSTL
. The contents of VSTL determine in which
VSTH
s
C
F
is the time within t
INE ADJUSTMENT
OARSE ADJUSTMENT
f
xtal
+
1
Pulse duration
PCA84C646; PCA84C846
64
32 and 96
16, 48, 80 and 112
8, 24, 40, 56, 72, 88, 104 and 120
4, 12, 20, 28, 36, 44, 52...116 and 124
2, 6, 10, 14, 18, 22, 26, 30...122 and 126
1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127
ADDITIONAL PULSE IN SUBPERIOD
3
subn
=
.
Preliminary specification
127 VSTH
–
--------
f
xtal
3
.