PCA84C646 Philips Semiconductors, PCA84C646 Datasheet - Page 28

• Manufacturer Part Number: PCA84C646
• Description: Microcontrollers for TV tuning control and OSD applications
• Manufacturer: Philips Semiconductors

Philips Semiconductors
12.4
This register selects the 4 display modes(Mode 0 to Mode 3); the active state of HSYNC and VSYNC and the output
polarity of the FB and VOW0 to VOW2 outputs. It also enables/disables the OSD clock (f
Table 30 Derivative Register 34
Table 31 Description of Derivative Register 34 bits
Table 32 Selection of Display Modes
1995 Jun 15
S1
Microcontrollers for TV tuning
control and OSD applications
0
0
1
1
BIT
7
Derivative Register 34 (CON4)
7
6
5
4
3
2
1
0
S0
0
1
0
1
Mode 0 No background mode (see Fig.21). The OSD fonts/characters are directly superimposed on
Mode 1 North-west shadowing mode (see Fig.22). Available only in the character size 2V/2H or 4V/4H
Mode 2 Box shadowing mode (see Fig.23). Box shadowing is to surround the character font by a
Mode 3 Frame shadowing mode (raster blanking; see Fig.24); background colour displayed on full
SYMBOL
EN
Hp
S1
S0
Vp
Bp
6
the TV video signals.
(V: horizontal line; H: OSD clock).The shadows of the characters are generated by placing a
light source on the North-west 45 degree direction (see also Figs 25 and 26). When designing
the character bit pattern, care must be taken that the shadows generated by this mode is only
within the cell boundary in vertical direction (see Figs 28 and 29 for details). But shadows
generated by this mode in horizontal direction has no boundary limitation (Fig.30).
12
dots are filled with background dots (see Fig.27).
screen where no bit patterns are on.The background colour is controlled by Derivative Register
37 and has 8 different colours; see Table 39.
These two bits are reserved.
Display mode select bits; see Table 32.
HSYNC signal polarity control bit (see Fig.19).
VSYNC signal polarity control bit (see Fig.19).
Output polarity control bit for FB, VOW0, VOW1 and VOW2 (see Fig.20).
OSD clock enable/disable bit.
18 dots box in background, i.e. within the character font cell; locations with no foreground
When Hp = 1; the active level of HSYNC is HIGH.
When Hp = 0; the active level of HSYNC is LOW (default state).
When Vp = 1; the active level of VSYNC is HIGH.
When Vp = 0; the active level of VSYNC is LOW (default state).
When Bp = 1; the polarity of FB, VOW0, VOW1 and VOW2 is HIGH (default state).
When Bp = 0; the polarity of FB, VOW0, VOW1 and VOW2 is LOW.
When EN = 1; the OSD clock is enabled.
When EN = 0; the OSD clock is disabled.
S1
5
S0
4
28
DISPLAY MODE
Hp
DESCRIPTION
3
PCA84C646; PCA84C846
Vp
2
OSD
).
Preliminary specification
Bp
1
EN
0