PCA84C646 Philips Semiconductors, PCA84C646 Datasheet - Page 8

• Manufacturer Part Number: PCA84C646
• Description: Microcontrollers for TV tuning control and OSD applications
• Manufacturer: Philips Semiconductors

Philips Semiconductors
6
The RESET pin is used as an active LOW input to initialize
the microcontroller to a defined state.
A Power-on-reset can be generated by using the
RC-circuit as shown in Fig.3.
An active reset can be generated by driving the RESET pin
from an external logic device. Such an active reset pulse
should not fall off before V
f
6.1
The RESET trip-voltage level is masked to 1.3 V in the
PCA84C646 and PCA84C846.
6.2
1995 Jun 15
xtal
Derivative Registers status; for details see Table 40
Program Counter: 00H
Memory Bank: 00H
Register Bank: 00H
Stack Pointer: 00H
All interrupts disabled
Timer/event counter 1 stopped and cleared
Timer prescaler modulo-32 (PS = 0)
Timer flag cleared
Serial I/O interface disabled (ESO = 0) and in slave
receiver mode
Idle and Stop mode cleared.
Microcontrollers for TV tuning
control and OSD applications
-dependent minimum operating voltage.
(1) To avoid overload of the internal diode, an external
RESET
diode should be added in parallel if C
Reset trip level
Reset status
( 100 k )
Fig.3 External components for RESET pin.
C
R
RESET
RESET
RESET
V
V
DD
SS
(1)
DD
has reached its
PCA84C646/846
RESET
internal reset
0.2 F.
MED172
8
7
7.1
The PCA84C646/PCA84C846 has eight PWM outputs for
analog controls of e.g. volume, balance, brightness and
saturation. These PWM outputs generate pulse patterns
with a repetition rate of
analog value is determined by the ratio of the HIGH-time
and the repetition time. A DC voltage proportional to the
PWM control setting is obtained by means of an external
integration network (low-pass filter).
The eight PWM outputs are specified as follows:
Figure 4 shows the block diagram of the 6-bit or 7-bit PWM
DAC. The polarity of the PWM0n output is selected as
shown in Table 2 by the polarity control bit P6LVL/P7LVL
(Derivative Register 23; see Table 25).
The PWM0n output shares the pin with a DP0n I/O line
under control of a PWMnE enable bit; for selection see
Table 3.
Figure 5 shows the 6 and 7-bit PWM0n output patterns
(non-inverted; P6LVL/P7LVL = 0).
The HIGH-time of a PWM0n output is
t
where:
Table 2 Polarity selection for the PWM0n output
Table 3 Selection of pin function: DP0n/PWM0n (note 1)
Note
1. n = 0 to 7.
HIGH
P6LVL/P7LVL
PWM00 to PWM03 outputs with 7-bit resolution
PWM04 to PWM07 outputs with 6-bit resolution.
(n = 0 to 7; Derivative Register 10 to 17; see Table 40)
t
0
PWMnDL = the contents of PWMn data latch
PWMnE
ANALOG CONTROL
= 1/f
= PWMnDL
6 and 7-bit PWM outputs (PWM00 to PWM07)
1
0
1
0
PWM
; f
PWM
PCA84C646; PCA84C846
=
t
1
0
3
1
64
f
xtal
f
PWM0n output
.
PWM
not inverted
FUNCTION
POLARITY
DP0n I/O
inverted
Preliminary specification
or
1
128
f
PWM
. The