CS5126 Cirrus Logic, CS5126 Datasheet - Page 18

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CS5126

Manufacturer Part Number
CS5126
Description
16-Bit Stereo A/D Converter for Digital Audio
Manufacturer
Cirrus Logic
Datasheet

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RST - Reset, PIN 32.
Analog Inputs
AINL, AINR - Left and Right Channel Analog Inputs, PINS 19 and 24.
VREF - Voltage Reference, PIN 20.
Digital Outputs
STBY - Standby (Calibrating), PIN 5.
SDATA - Serial Output, PIN 15.
SSH1, SSH2 - Simultaneous Sample/Hold 1 and 2, PINS 10 and 11.
TRKL, TRKR - Tracking Left, Tracking Right, PINS 8 and 9.
Analog Outputs
REFBUF - Reference Buffer Output, PIN 21.
Miscellaneous
NC - No Connection, PIN 4.
TST1, TST2, TST3, TST4 - Test, PINS 17, 18, 26, 27.
18
When taken low, all internal digital logic is reset. Upon returning high, a full calibration
sequence is initiated which takes 34,584,480 master clock cycles to complete.
Analog input connections for the left and right input channels.
The analog reference voltage which sets the analog input range. Its magnitude sets both positive
and negative full-scale.
Indicates calibration status after reset. Remains low throughout the calibration sequence and
returns high upon completion.
Presents each output data bit on a falling edge of the SCLK input. Data is valid to be latched
on the rising edge of SCLK.
Used to control external sample/hold amplifier(s) to achieve simultaneous stereo sampling.
Indicate the end of a conversion cycle. Either TRKL or TRKR falls at the end of a conversion
cycle depending on the status of L/R and which channel is to be tracked.
Reference buffer output. A 0.1 F ceramic capacitor must be tied between this pin and VA-.
Must be left floating for proper operation.
Allow access to the CS5126’s test functions which are reserved for factory use. Must be tied to
VD+.
CS5126
DS32F1

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