CS5126 Cirrus Logic, CS5126 Datasheet - Page 7

• Manufacturer Part Number: CS5126
• Description: 16-Bit Stereo A/D Converter for Digital Audio
• Manufacturer: Cirrus Logic

each conversion finishes determines which chan-
nel is acquired and tracked. The L/R input must
remain valid at least until 30ns before the next
falling transition on HOLD.
As shown in the timing diagram in Figure 3, the
CS5126 uses pipelined data transmission. That
is, data from a particular conversion transmits
during the next conversion cycle. The serial
clock input, SCLK, is derived by dividing the
master clock by 16. The MSB (most-significant-
bit) will be stable on the first rising edge of
SCLK after a falling transition on HOLD. With
a serial clock of f
output bits will span an entire conversion and
acquisition cycle.
DS32F1
L/R (i)
HOLD (i)
SCLK (i)
SDATA (o)
Internal
Status
Analog In
Analog In
Right Ch.
Left Ch.
LSB
clk
/16, transmission of all 16
+5V
-5V
MSB
Reference
Anti Alias
Anti Alias
Rch Conv.
Voltage
Filter
Filter
1 F
Figure 2. Stereo Mode Connection Diagram
Left Channel Data
+
200
200
+ 1 F
1 nF
1 nF
Figure 3. Stereo Mode Timing
0.1 F
Lch Acq.
0.1 F
0.1 F
AINL
AINR
VREF
AGND
REFBUF
LSB
VA+
VA-
STEREO MODE PERFORMANCE
As illustrated in Figure 4, the CS5126 typically
provides 92dB S/(N+D) and 0.001% THD. Un-
like conventional successive-approximation
ADC’s, the CS5126’s signal-to-noise and dy-
namic range are not limited by differential non-
linearities (DNL) caused by calibration errors.
Rather, the dominant noise source is broadband
thermal noise which aliases into the baseband.
This white broadband noise also appears as an
idle channel noise of 1/2 LSB (rms).
CS5126
MSB
10
10
Lch Conv.
SDATA
SLEEP
VD+
CLKIN
DGND
VD-
HOLD
SCLK
Right Channel Data
L/R
0.1 F
f
f
f
f
0.1 F
clk
clk
clk
clk
/512
/256
/16
Rch Acq.
+ 1 F
LSB
+
1 F
MSB
CS5126
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