CS5126 Cirrus Logic, CS5126 Datasheet - Page 25

• Manufacturer Part Number: CS5126
• Description: 16-Bit Stereo A/D Converter for Digital Audio
• Manufacturer: Cirrus Logic

Sampling Clock Generation Logic
The CS5126 requires an external serial clock to
clock out the data. The CDB5126 board has the
logic necessary to generate the master clock,
HOLD, L/R, and SCLK to allow fast evaluation
of the ADC. In most systems, these timing sig-
nals will be available from the main timing
section, typically generated by a logic array of
some variety. HOLD may be brought in exter-
nally via a
BNC, optionally terminated by R29. SCLK and
L/R select may be brought in externally via test
points and removing jumpers.
Figure 5 shows the on-board clock generation
circuitry. U7 (74HC4040) produces binary di-
vided ratios of the 24.576 MHz master clock. Q4
generates a 1.5 MHz clock, which is used for
SCLK. Q8 generates a 96 kHz clock, used for
HOLD, and Q9 generates a 48 kHz clock, option-
DS32DB5
U11, pin 8
+5VL
R16
47 k
p.4
C28
0.1 F
1
0
12
13
P12
U6
Crystal
Oscillator
Module
R18
47 k
+5VL
U11
14
OUT
7
(CLKIN)
11
8
P1
P4
0
1
2
15
14
12
10
11
1
8
P10
Q12
Q11
Q10
Q9
CLK
RST
+5VL
U7
16
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
0.1 F
C29
9
7
6
5
3
2
4
13
R28
470
Figure 5. Timing Generator
47 k
R19
(HOLD)
P2
12
11
5
6
3
4
2
1
U12
14
7
74HC30
8
ally used to toggle L/R select. This set of clocks
causes the CS5126 to continuously convert, gen-
erating a continuous stream of serial data bits. To
correctly identify the last bit of each word, U12
produces a pulse only when Q4, Q5, Q6, Q7, Q8,
and optionally Q9 are all high. This state is
latched by U10A to prevent any glitches, and the
resulting signal (attached to TP18) is used to
latch the U8-U9 shift registers.
Serial to Parallel Conversion
Figure 6 shows the serial to parallel conversion
circuit. Two 74HC595 shift register/latches con-
nected in series with SDATA assemble 16-bit,
parallel words, clocked by SCLK. As discussed
above, the outputs are latched inside the
74HC595 at the end of each 16-bit word. The
outputs are brought out to a 40-way header (P5).
Only low capacitance, twisted pair, ribbon cable
should be used.
C32
0.1 F
R16, p.3
47 k
2
Shift CLK
1
U8, U9
U11
P3
14
7
P9
74HC00
3
C30
0.1 F
14
R16, p.5
47 k
J
1
K
74HC73
U10A
3
CLR
CDB5126
2
11
4
Q
Q
12
13
C31
0.1 F
Latch CLK
0
U8, U9
1
P7
25