CS51311GD14 Cherry Semiconductor Corporation, CS51311GD14 Datasheet - Page 14

• Manufacturer Part Number: CS51311GD14
• Description: Synchronous CPU Buck Controller for 12V and 5V Applications
• Manufacturer: Cherry Semiconductor Corporation

C
impedance is very low, the V
plateaus during rapid changes in the drain-to-source volt-
age.
The most important aspect of FET performance is the Static
Drain-To-Source On-Resistance (R
regulator efficiency and FET thermal management require-
ments. The On-Resistance determines the amount of cur-
rent a FET can handle without excessive power dissipation
that may cause overheating and potentially catastrophic
failure. As the drain current rises, especially above the con-
tinuous rating, the On-Resistance also increases. Its posi-
tive temperature coefficient is between +0.6%/C and
+0.85%/C. The higher the On-Resistance the larger the
conduction loss is. Additionally, the FET gate charge
should be low in order to minimize switching losses and
reduce power dissipation.
Both logic level and standard FETs can be used. The refer-
ence designs derive gate drive from the 12V supply, which
is generally available in most computer systems and uti-
lizes logic level FETs.
Voltage applied to the FET gates depends on the applica-
tion circuit used. Both upper and lower gate driver outputs
are specified to drive to within 1.5V of ground when in the
low state and to within 2V of their respective bias supplies
when in the high state. In practice, the FET gates will be
driven rail-to-rail due to overshoot caused by the capaci-
tive load they present to the controller IC.
Step 7a - Selection of the switching (upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
The maximum RMS current through the switch can be
determined by the following formula:
I
where
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
where
The upper MOSFET switching losses are caused during
MOSFET switch-on and switch-off and can be determined
by using the following formula:
RMS(H)
DG
I
I
I
D = Duty Cycle.
P
I
R
RMS(H)
L(PEAK)
L(VALLEY)
RMS(H)
RMS(H)
DS(ON)
(I
GATE
=
(I
L(PEAK)
= maximum switching MOSFET RMS current;
= maximum switching MOSFET RMS current;
= inductor peak current;
= switching MOSFET conduction losses;
= FET drain-to-source on-resistance
= C
= inductor valley current;
dg
P
2
dV
RMS(H)
+ (I
dg
L(PEAK)
/dt). Unless the gate-drive
= I
RMS(H)
× I
GS
L(VALLEY)
waveform commonly
3
2
× R
DS(ON)
DS(ON)
) + I
), which effects
Application Information: continued
L(VALLEY)
2
× D
,
14
where
The total power dissipation in the switching MOSFET can
then be calculated as:
where
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature
can be calculated:
where
Step 7b: Selection of the synchronous (lower) FET
The switch conduction losses for the lower FET can be cal-
culated as follows:
where
The synchronous MOSFET has no switching losses, except
for losses in the internal body diode, because it turns on
into near zero voltage conditions. The MOSFET body
diode will conduct during the non-overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
where
P
P
V
I
t
switching characteristics performance curve);
t
switching characteristics performance curve);
T = 1/F
P
P
P
P
T
T
P
R
P
I
D = Duty Cycle;
R
P
V
I
Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-
to-GATE(L) delay (from CS51311 data sheet Electrical
P
OUT
RISE
FALL
OUT
LOAD
SWH(ON)
SWH(OFF)
HFET(TOTAL)
RMSH
SWH(ON)
SWH(OFF)
J
A
HFET(TOTAL)
RMSL
SWL
θJA
DS(ON)
IN
RMSL
SD
= FET junction temperature;
= ambient temperature;
= input voltage;
P
= lower FET source-to-drain voltage;
P
= upper FET junction-to-ambient thermal resistance
= MOSFET rise time (from FET manufacturer’s
= load current;
= load current;
= MOSFET fall time (from FET manufacturer’s
= lower FET switching losses;
HFET(TOTAL)
SWL
= load current
= lower MOSFET conduction losses;
= I
= upper MOSFET switch conduction Losses;
SW
P
= lower FET drain-to-source on-resistance.
SWH
RMS
= upper MOSFET switch-on losses;
= upper MOSFET switch-on losses;
= V
= upper MOSFET switch-off losses;
= upper MOSFET switch-off losses.
= period.
T
= total switching (upper) MOSFET losses;
J
= total switching (upper) FET losses;
2
SD
= P
=
= T
× R
V
× I
SWH(ON)
= P
A
DS(ON)
IN
LOAD
+ [P
× I
RMSH
OUT
HFET(TOTAL)
= [I
× non-overlap time × F
+ P
+ P
× (t
OUT
6T
SWH(OFF)
SWH(ON)
RISE
× (1 − D)]
+ t
× R
FALL
+ P
θJA
SWH(OFF)
],
)
,
2
× R
SW
DS(ON)
,
,
,