ADV7160 Analog Devices, ADV7160 Datasheet - Page 17

• Manufacturer Part Number: ADV7160
• Description: 96-Bit/ 220 MHz True-Color Video RAM-DAC
• Manufacturer: Analog Devices

REV. 0
CLOCK CONTROL SIGNALS
LOADOUT
The ADV7160/ADV7162 generates a LOADOUT control sig-
nal which runs at a divided down frequency of the pixel
CLOCK. The frequency is automatically set to the pro-
grammed multiplex rate, controlled by CR37 and CR36 of
Command Register 3.
The LOADOUT signal is used to directly drive the LOADIN
pixel latch signal of the ADV7160/ADV7162. This is most sim-
ply achieved by tying the LOADOUT and LOADIN pins to-
gether. Alternatively, the LOADOUT signal can be used to
drive the frame buffer’s shift clock signals, returning to the
LOADIN input delayed with respect to LOADOUT.
If it is not necessary to have a known fixed number of pipeline
delays, then there is no limitation on the delay between
LOADOUT and LOADIN (LOADOUT(1) and
LOADOUT(2)). LOADIN and Pixel Data must conform to
the setup and hold times (t
If however, it is required that the ADV7160/ADV7162 has
a fixed number of pipeline delays (t
LOADIN must conform to timing specifications t
illustrated in Figures 5 to 10.
Figure 16. Clock Control Circuit of the ADV7160/ADV7162
PRGCKOUT
LOADOUT
TRISYNC
SCKOUT
f
f
f
PLL REF
LOADIN
CLOCK
CLOCK
BLANK
LOADOUT
LOADOUT
LOADOUT
SCKIN
SYNC
= f
= f
= f
CLOCK
CLOCK
CLOCK
M IS A FUNCTION OF MULTIPLEX RATE
N IS INDEPENDENTLY PROGRAMMABLE
PLL
ECL
TTL
TO
M = 8 IN 8:1 MULTIPLEX MODE
M = 4 IN 4:1 MULTIPLEX MODE
M = 2 IN 2:1 MULTIPLEX MODE
N = (4, 8, 16, 32)
TO COLOR DATA
MULTIPLEXER
8
/8
/4
/2
and t
S
E
L
E
C
T
DIVIDE BY
9
N ( N)
ADV7160/
).
ADV7162
8:1 multiplex mode
4:1 multiplex mode
2:1 multiplex mode
PD
LATCH
) LOADOUT and
EN
DIVIDE BY
M ( M)
10
and –t
11
as
–17–
Pipeline Delay and Onboard Calibration
The ADV7160/ADV7162 has a fixed number of pipeline delays
(t
fixed number of pipeline delays is not a requirement, timings t
and –t
there is no restriction on LOADIN to LOADOUT timing. If
timings t
though with an increased number of pipeline delays. The
ADV7160/ADV7162 has on-board calibration circuitry which
synchronizes pixel data and LOADIN with the internal
ADV7160/ADV7162 clocking signals. Calibration can be per-
formed in two ways. During the device’s initialization sequence
by toggling two bits of the Mode Register, MR10 followed by
MR15 or by writing a “1” to Bit CR10 of Command Register 1
and a “0” to MR15 which executes a calibration on every
Vertical Sync.
PRGCKOUT
The PRGCKOUT control signal outputs a user programmable
clock frequency. It is a divided down frequency of the pixel
CLOCK (see Figure 11). The rising edge of PRGCKOUT is
synchronous to the rising edge of LOADOUT.
where N = 4, 8, 16 or 32.
One application of the PRGCKOUT is to use it as the master
clock frequency of the graphics subsystems processor or
controller.
SCKIN, SCKOUT
These video memory signals are used to minimize external sup-
port chips. Figure 18 illustrates the function that is provided.
An input signal applied to SCKIN is synchronously AND-ed
with the video blanking signal (BLANK). The resulting signal
is output on SCKOUT. Figure 12 of the Timing Waveform
section shows the relationship between SCKOUT, SCKIN and
BLANK.
LOADOUT
LOADIN
PD
BUFFER
FRAME
VIDEO
), so long as timings t
11
10
can be ignored, a calibration cycle must be run and
Figure 18. SCKOUT Generation Circuit
and –t
Figure 17. LOADOOUT vs Pixel Clock
SCKOUT
BLANK
SCKIN
SYNC
11
f
PRGCKOUT
LOADOUT
LOADIN
PIXEL
DATA
are not met, the part will function correctly
ADV7160/
ADV7162
10
and –t
= f
ADV7160/ADV7162
CLOCK
LOADOUT(1)
LOADOUT(2)
11
BUFFER
FRAME
VIDEO
/N
are met. However, if a
ENABLE
LATCH
LOADOUT(1)
LOADOUT(2)
DELAY
LOADOUT
LOADIN
PIXEL
DATA
ADV7160/
ADV7162
10