ADV7160 Analog Devices, ADV7160 Datasheet - Page 40
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ADV7160
Manufacturer Part Number
ADV7160
Description
96-Bit/ 220 MHz True-Color Video RAM-DAC
Manufacturer
Analog Devices
Datasheet
1.ADV7160.pdf
(44 pages)
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ADV7160/ADV7162
Signature Register
The ADV7160/ADV7162 contains onboard circuitry that enables
both device and system level test diagnostics. The ADV7160/
ADV7162 has a signature analyzer in the pixel datapath, just
before the DAC decoders. The signature analyzer consists of a
33-bit linear feedback shift register. The 30-bit pixel value is
fed as a parallel input into the analyzer. The signature analyzer
only accumulates a signature during active display time when
BLANK is high. Bit CR45 to CR47 of Command Register 4
control the signature analyzer. When CR45 of Command Reg-
ister 4 is set to Logic “1,” the clock to the signature analyzer is
enabled. Toggling CR46 low and then high resets the signature
analyzer. This is done to give a known starting point before ac-
quiring a signature. CR47 of Command Register 4 controls the
feedback inputs to the analyzer. When CR47 of Command
Register 4 is a Logic “0,” the feedback is disabled and on each
clock cycle, the 30-bit pixel value is latched directly into the
analyzer. To acquire a signature as the analyzer is clocked,
CR47 of Command Register 4 is set to Logic “1.” To acquire a
signature the following procedure must be followed:
1. CR45 and CR47 of Command Register 4 are set to Logic
2. A signature is acquired during the following active screen.
“1” during vertical retrace and CR46 of Command Register
4 is toggled to reset the analyzer.
REGISTER I/P
SIGNATURE
S19
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
'0'
'0'
SIGNATURE
CELL
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
SIGNATURE ANALYZER
APPENDIX 5
–40–
CR42
CR42
3. CR45 of Command Register 4 is set to Logic “0” during the
The signature analyzer is read from control registers 010H to
013H. These are read only 10-bit registers. The access to these
registers depends whether the part is in 8-bit or 10-bit data bus
mode and operates in the same way as accessing the color palette.
Address
Register CONTROL
(A10–A0) REGISTERS
0013H
0012H
0011H
0010H
S19
B0
S32
following vertical retrace and the acquired signature is read.
At least 20 clock cycles should be allowed for the final pixels
of the frame to travel down the pipeline of the ADV7160/
ADV7162 before the signature clock is disabled.
Signature Misc Register 0
Signature Blue Register S10 S9
Signature Green Register S20 S19 S18 S17 S16 S15 S14 S13 S12 S11
Signature Red Register
CONTENTS
S30 S29 S28 S27 S26 S25 S24 S23 S22 S21
0
0
S8
0
S7
S0
S1
0
S6
0
S5
0
S4
S32 S31 S0
S3
REV. 0
S2
S1