DAC7802K Burr-Brown Corporation, DAC7802K Datasheet - Page 5

• Manufacturer Part Number: DAC7802K
• Description: Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
• Manufacturer: Burr-Brown Corporation

DAC7800
TIMING CHARACTERISTICS
V
DAC7801
LOGIC TRUTH TABLE
BLOCK DIAGRAM
DD
UPD
X = Don’t care.
CLR
WR
CS
A1
A0
= +5V, V
CLR
PARAMETER
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
1
1
0
1
1
1
1
1
1
— Data Setup Time
— Data Hold Time
— Chip Select to CLK,
— Chip Select to CLK,
— CLK Pulse Width
— Clear Pulse Width
— Update Pulse Width
— CLK Edge to UPD A
19
16
15
18
17
Update, Data Setup Time
Update, Data Hold Time
or UPD B
5
REF A
DAC7801
V
20
UPD
= V
DD
X
1
1
1
1
1
1
0
0
REF B
DB7–DB0
14
(CONT)
= +10V, T
6
CS
1
X
X
0
0
0
0
1
0
DAC A
DAC B
Input
Input
Reg
Reg
MS
MS
DAC A Register
DAC B Register
4
4
A
MINIMUM
= –40 C to +85 C.
15ns
15ns
15ns
40ns
40ns
40ns
40ns
15ns
DAC B
DAC A
12
12
WR
X
1
X
0
0
0
0
0
0
DAC A
DAC B
Input
Input
Reg
Reg
LS
LS
UPD A
UPD B
8
DATA
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns. (2) Tim-
ing measurement reference level is V + V
8
CLK
CLR
CS
DGND
12
A1
X
X
X
0
0
1
1
X
X
21
22
23
24
2
1
3
4
t
3
I
AGND A
R
V
V
R
I
AGND B
OUT A
OUT B
FB A
REF A
REF B
FB B
t
1
A0
X
X
X
X
X
0
1
0
1
t
2
5
FUNCTION
No Data Transfer
No Data Transfer
All Registers Cleared
DAC A LS Input Register Loaded with DB7–DB0 (LSB)
DAC A MS Input Register Loaded with DB3 (MSB)–DB0
DAC B LS Input Register Loaded with DB7–DB0 (LSB)
DAC B MS Input Register Loaded with DB3 (MSB)–DB0
DAC A, DAC B Registers Updated Simultaneously from Input Registers
DAC A, DAC B Registers are Transparent
PIN CONFIGURATION
t
5
IH
2
IL
.
AGND A
DGND
V
I
R
OUT A
REF A
DB0
DB1
DB2
DB3
DB4
DB5
FB A
CS
10
11
12
1
2
3
4
5
6
7
8
9
DAC7800, 01, 02
DAC7801
Top View
DIP
t
8
t
7
24
23
22
21
20
19
18
17
16
15
14
13
R
t
4
F
AGND B
I
R
V
V
UPD
WR
CLR
A1
A0
DB7
DB6
OUT B
FB B
REF B
DD
t
6
0V
5V
0V
5V
5V
5V
®