SAA7380GP Philips Semiconductors, SAA7380GP Datasheet - Page 23

• Manufacturer Part Number: SAA7380GP
• Description: Error correction and host interface IC for CD-ROM ELM
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.7.24
This read only register is only available in the ATAPI mode;
it is the ATAPI command register and is used to transfer
commands from the host to the SAA7380.
The CMDI interrupt is generated when;
The BSY bit in the ASTAT register is also set under these
conditions. If the sub-CPU reads this register while CMDI
is asserted then it will be negated.
7.7.28
Table 21 ADRSEL register bits
Bit 4 of this register is the DRV bit. When this bit is the same as the RDRV bit in the DTCTR register then the SAA7380
will be the selected ATAPI drive and will respond to host commands and produce host interrupts.
7.7.29
This register is the ATAPI Interrupt Reason register.
7.7.30
This read only register is the ATAPI Features register.
7.7.31
This write only register is the ATAPI Error register.
1996 Apr 25
The host writes to this register while the SAA7380 is the
selected drive (the DRV bit in the ADRSEL register is
equal to the RDRV bit in the DTCTR register)
The host writes the execute drive diagnostic command
(90H) to this register.
Error correction and host interface IC for
CD-ROM (ELM)
BIT 7
1
ACMD
ADRSEL
AINTR
AFEAT
AERR
BIT 6
1
BIT 5
1
BIT 4
DRV
23
7.7.25
This write only register is the ATAPI Drive Address
register.
7.7.26
This register is the ATAPI Sector Number register.
7.7.27
This read only register is the ATAPI Device Control
register. If the SRSTI interrupt is asserted then reading this
register will negate it.
7.7.32
The DTCTR register controls data transfer flows in the host
Interface block. On reset this register is cleared to all zeros
except for the RDRV bit which is set to logic 1. This means
that the SAA7380 will be set to drive 1 after a reset.
There are several possible data transfers through the
SAA7380 host Interface block and these are selected
using the TRANT bits. The transfers are described in the
Table 23.
BIT 3
ADRADR
ASAMT
ADCTR
DTCTR - D
BIT 2
ATA
T
RANSFER
BIT 1
Preliminary specification
C
ONTROL
SAA7380
R
EGISTER
BIT 0