ADE7758 Analog Devices, ADE7758 Datasheet - Page 24

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

ADE7758
ZERO-CROSSING DETECTION
The ADE7758 has zero-crossing detection circuits for each of
the voltage channels (VAN, VBN, or VCN). Figure 51 shows
how the zero-cross signal is generated from the output of the
ADC of the voltage channel.
The zero-crossing interrupt is generated from the output of
LPF1. LPF1 has a single pole at 260 Hz (CLKIN = 10 MHz).
As a result, there is a phase lag between the analog input signal
of the voltage channel and the output of LPF1. The phase
response of this filter is shown in the Voltage Channel Sampling
section. The phase lag response of LPF1 results in a time delay
of approximately 1.1 ms (@ 60 Hz) between the zero-crossing
signal on the voltage inputs of the zero-crossing signal. Note
that the zero-crossing signal is used for the line cycle accumula-
tion mode, zero-crossing interrupt, and line period/frequency
measurement.
When one phase crosses from negative to positive, the
corresponding flag in the interrupt status register (Bit 9 to
Bit 11) is set to Logic 1. An active low in the IRQ output also
appears if the corresponding ZX bit in the interrupt mask
register is set to Logic 1. Note that only zero crossing from
negative to positive will generate an interrupt.
The flag in the interrupt status register is reset to 0 when the
interrupt status register with reset (RSTATUS) is read. Each
phase has its own interrupt flag and mask bit in the interrupt
register.
Zero-Crossing Timeout
Each zero-crossing detection has an associated internal timeout
register (not accessible to the user). This unsigned, 16-bit register
is decreased by 1 every 384/CLKIN seconds. The registers are
reset to a common user programmed value, i.e., the zero-
VAN,
VBN,
VCN
0.908
1.0
Figure 51. Zero-Crossing Detection on Voltage Channels
GAIN[6:5]
×
1,
PGA
×
2,
×
24.8
4
°
REFERENCE
@ 60Hz
READ RSTATUS
ADC
f
–3dB
LPF1
= 260Hz
ANALOG VOLTAGE
WAVEFORM
(VAN, VBN, OR VCN)
DETECTOR
CROSSING
ZERO-
IRQ
LPF1
OUTPUT
Rev. A | Page 24 of 68
crossing timeout register (ZXTOUT[15:0], Address 0x1B),
every time a zero crossing is detected on its associated input.
The default value of ZXTOUT is 0xFFFF. If the internal register
decrements to 0 before a zero crossing at the corresponding
input is detected, it indicates an absence of a zero crossing in
the time determined by the ZXTOUT[15:0]. The ZXTOx
detection bit of the corresponding phase in the interrupt status
register is then switched on (Bit 9 to Bit 11). An active low on
the IRQ output also appears if the ZXTOx mask bit for the
corresponding phase in the interrupt mask register is set to
Logic 1. Figure 52 shows the mechanism of the zero-crossing
timeout detection when the line voltage A stays at a fixed dc
level for more than CLKIN/384 × ZXTOUT[15:0] seconds.
PHASE COMPENSATION
When the HPF in the current channel is disabled, the phase
error between the current channel (IA, IB, or IC) and the
corresponding voltage channel (VA, VB, or VC) is negligible.
When the HPF is enabled, the current channels have phase
response (see Figure 53 and Figure 54). Figure 55 is the magni-
tude response of the filter. The phase response is almost 0 from
45 Hz to 1 kHz. The frequency band is sufficient for the
requirements of typical energy measurement applications.
However, despite being internally phase compensated, the
ADE7758 must work with transducers that may have inherent
phase errors. For example, a current transformer (CT) with a
phase error of 0.1° to 0.3° is not uncommon. These phase errors
can vary from part to part, and they must be corrected in order
to perform accurate power calculations. The errors associated
with phase mismatch are particularly noticeable at low power
factors. The ADE7758 provides a means of digitally calibrating
these small phase errors. The ADE7758 allows a small time delay
or time advance to be introduced into the signal processing
chain in order to compensate for the small phase errors.
REGISTER VALUE
16-BIT INTERNAL
DETECTION BIT
ZXTOUT[15:0]
CHANNEL A
VOLTAGE
ZXTOA
Figure 52. Zero-Crossing Timeout Detection
RSTATUS
READ