ADE7758 Analog Devices, ADE7758 Datasheet - Page 7

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, T
Table 2.
Parameter
Write Timing
Read Timing
1
2
3
4
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
See the timing diagrams in
Measured with the load circuit in
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
3
4
4
Specification
50
50
50
10
5
900
50
100
1.1
50
30
100
10
100
10
Figure 3
Figure 2
and
Figure 4
Unit
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
µs (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
and defined as the time required for the output to cross 0.8 V or 2.4 V.
and the
1, 2
ADE7758 Serial Interface
Test Conditions/Comments
CS falling edge to first SCLK falling edge.
SCLK logic high pulse width.
SCLK logic low pulse width.
Valid data setup time before falling edge of SCLK.
Data hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS hold time after SCLK falling edge.
Minimum time between read command (i.e., a write to communication register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the communications register.
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS.
Figure 2. Load Circuit for Timing Specifications
TO OUTPUT
PIN
Rev. A | Page 7 of 68
50pF
C
L
1.6mA
200µA
section.
I
I
OL
OH
2.1V
MIN
to T
MAX
= −40°C to +85°C.
ADE7758