ADE7758 Analog Devices, ADE7758 Datasheet - Page 27

• Manufacturer Part Number: ADE7758
• Description: Poly Phase Multifunction Energy Metering IC with Per Phase Information
• Manufacturer: Analog Devices

Note that the number of half-line cycles is based on counting
the zero crossing of the voltage channel. The ZXSEL[2:0] bits in
the LCYCMODE register determine which voltage channels are
used for the zero-crossing detection. The same signal is also
used for line cycle energy accumulation mode if activated (see
the Line Cycle Accumulation Mode Register (0x17) section).
Overvoltage Detection Interrupt
Figure 59 illustrates the behavior of the overvoltage detection.
PKV INTERRUPT FLAG
Note that the content of the VPINTLVL[7:0] register is
equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform
samples; therefore, setting this register to 0x92 represents
putting the peak detection at full-scale analog input. Figure 59
shows a voltage exceeding a threshold. By setting the PKV flag
(Bit 14) in the interrupt status register, the overvoltage event is
recorded. If the PKV enable bit is set to Logic 1 in the interrupt
mask register, the IRQ logic output goes active low (see the
ADE7758 Interrupts section).
Multiple phases can be activated for peak detection. If any
of the active phase produces waveform samples above the
threshold, the PKV flag in the interrupt status register is set.
The phase in which overvoltage is monitored is set by the
PKIRQSEL[5:7] bits in the MMODE register (see Table 15).
PHASE SEQUENCE DETECTION
The ADE7758 has on-chip phase sequence error detection
interrupt. If the zero crossing of Phase A is not followed by
Phase C but by Phase B, the SEQERR bit (Bit 19) in the STATUS
register is set. If SEQERR, Bit 19, is set in the mask register, the
IRQ logic output goes active low (see the ADE7758 Interrupts
section). The following figure depicts how the interrupt is
issued in two different configurations. Note that if it is desired
to have the interrupt occur when Phase A is followed by
Phase B and not Phase C, then the analog inputs for Phase B
and phase C should be swapped. In this case, the Phase B
(BIT 14 OF STATUS
READ RSTATUS
VPINTLVL[7:0]
REGISTER)
REGISTER
Figure 59. ADE7758 Overvoltage Detection
VOLTAGE PEAK WAVEFORM BEING MONITORED
(SELECTED BY PKIRQSEL[5:7] IN MMODE REGISTER)
PKV RESET LOW
WHEN RSTATUS
REGISTER IS READ
Rev. A | Page 27 of 68
voltage input should be wired to the VCP pin and the phase C
voltage input should be wired to the VBP pin.
WAVEFORMS
POWER-SUPPLY MONITOR
The ADE7758 also contains an on-chip power-supply monitor.
The analog supply (AVDD) is monitored continuously by the
ADE7758. If the supply is less than 4 V ± 5%, the ADE7758
goes into an inactive state, that is, no energy is accumulated
when the supply voltage is below 4 V. This is useful to ensure
correct device operation at power-up and during power-down.
The power-supply monitor has built-in hysteresis and filtering.
This gives a high degree of immunity to false triggering due to
noisy supplies. Figure 61 shows the behavior of the ADE7758
when the voltage of AVDD falls below the power-supply
monitor threshold. The power supply and decoupling for the
part should be designed such that the ripple at AVDD does not
exceed 5 V ± 5% as specified for normal operation.
CALCULATIONS
WAVEFORMS
CROSSINGS
CROSSINGS
VOLTAGE
VOLTAGE
INTERNAL
ZERO
ZERO
ADE7758
AV
A
A
DD
5V
4V
0V
A = 0°C
A = 0°C
Figure 61. On-Chip Power-Supply Monitoring
INACTIVE
C
B
SEQERR BIT OF STATUS REGISTER IS NOT SET
Figure 60. Phase Sequence Detection
SEQERR BIT OF STATUS REGISTER IS SET
C = –120°C
B = –120°C
B
C
A
A
ACTIVE
TIME
B
C
B = 120°C
C = 120°C
C
B
A
A
INACTIVE
C
B
ADE7758
C
B