MC6800 Motorola, MC6800 Datasheet - Page 25

• Manufacturer Part Number: MC6800
• Description: 8-BIT MICROPROCESSING UNIT (MPU)
• Manufacturer: Motorola

nodes, the address obtained
~umerical address.
)Iemented for the MPU’S branch instructions,
nemory location relative to the Program Counter’s current
Dcation. Branch instructions generate two bytes of machine
:ode, one for the instruction
‘relative” address (see Figure 32). Since it is desirable to be
ible to branch in either direction, the 8-bit address byte is in-
naining
)ranch range is computed with respect to the next instruc-
iatisfied. Since two bytes are generated, the next instruction
s located at PC + 2. If D is defined as the address of the
)ranch destination,
)r
vithin – 125 to + 1.29 memory locations of the branch in-
truction
erpreted as a signed 7-bit value; the 8th bit of the operand is
rested as a sign bit, “O”= plus and “1”=
esults in a relative addressing range of * 127 with respect to
he location of the branch instruction
ion that would be executed if the branch conditions are not
hat is, the destination
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
PSH
PUL
TSX
TX$~~~W ““
RTS
DES
DEX
INS
INX
Relative Address Mode – In both the Direct and Extended
..,,
and I nmructions
y;.
Addre*
\**,, ,.~.’~kq~,,.’
*$,f.. ‘ :%”
SBA
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
*Y.,
.. . . ‘k~:+.},t~$
seven bits represent
itself. For transferring
$~” ... “J~
,.*T. “‘,?.. ‘
TAB
TST
(PC+2)–
SEC
SE I
SEV
TAP
TBA
TPA
Mode
‘-? ; *-{., J .~ .~.ikb
:.$
,... “’i:.*
-$:.
Y
PC–125<D~PC+129
.3..,,, ,.
the range is then:
~:’,$.,j$:t
~~.$,,
The
.+ ~ @*” ~}
.:!
@
‘\~\ \\t\*.’
127SD S(PC+2)+127
$“
.
,{,: .-~
of the branch instruction
Cycles
.,
\\,
Relative
2
4
4
4
4
5
>,.
.,.
?4>,, ~j$ ,
~,q ~p.~ #
., .
by the MPU is an absolute
M070ROLA
the numerical
control beyond this range,
Cycle
g 3 ‘$$,“’” ,
opcode
.,t~,.:! ,),,,$
TABLE 6 – INHERENT MODE CYCLE-BY-CYCLE~~~~*lON
#
1
2
2
3
4
2
3
4
2
3
4
2
3
4
2
3
4
5
1
1 ,/ S* ‘$~~~?.$OP Code Address
1
1
1
addressing
VMA
itself, However, the
Lina
0
o
Q
0
0
1
1
1
1
~..~<f; ~~~~w Register Contents
,
‘
0
1
1
0
1
0
1
1
1
1
1
1
and one for the
*$~~$~~us
minus. The re-
~~.~~$$e
Op Code Address
OP Code Addrass + 1 ~*.st,&$f~
0 p$**j$dHress
Op Code Addrass + 1
Stack Pointer
Stack Pointer – 1
Op Code Address
Stack Pointer
OP Code Address
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Op Code Address+
New Index Register
Op Code Address
OP Code Address+
New Stack Pointer
OP Code Address+
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Index Register
value.
mode,
specifies a
must be
..*Y- . “’?.
:$.>,
Register Contents
This
Address+
,~~ ~i~ . ,
im-
~~~ ~ ,
.fi
Address Bus
,\,,,.\
,
25
>~:k(.’
Semiconductor
‘!><::+:$<>
~,.;*:~\,
I
1
1
1
.,?-
~.i:
Zero bit in the Condition Code Register. If that bit is “O,” in-
with the next instruction (in location WIO in Figure 32). If the
control program is normally in read-only memory #ti~$@not
operation is shown in Table 10 for relatig& a~Q@ssing.
the numerical address is variable qnd d~ends
.c:.~ ~ *,:r,
the unconditional
and return from subroutine
dicating
previous result was zero, the branch condition
and the MPU adds the offset, 15 in this case, to PC+ 2 and
branches to location W25 for the next instruction.
Iy direct the MPU to one point or another in the contro$.:~ro-
gram depending
be changed, the relative address used in execu@~~@t&ranch
instructions
contents of the Index Register@~~$ource statement such as
causes the M PU,:~q stalk the contents of accumulator
BEQ (Branch if result of last instruction was zero), it tests the
,,.t,,,,., .l’:.+
The branch instructions allow the programmer to efficient-
Indexed Addressing
In Figure 32, when the MPU encounters the opcode for
..- ,
.,, .<,; ,,,
.$.
Operator
,%
STAA
,:~, ,@ ~~’lw
,,+?
a non-zero result, the MPU continues
~ t.:.:~’
.r]i,
is a constant
., $:.?;,\
Lina
.tJ;., .,~<{y..,\\
on the outcome of test results. ~W~%e
1
1
o
Operan~*~~~
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
jump (JMP), jump to subroutine
Products Inc.
., )
X
*\+~*%\.g;~
Op Code
Op Code of Next
Op Code
Op Code
Op Code of Next Instruction
Op Code of Next Instruction
Accumulator
Accumulator
Op Code
Op Code of Next instruction
Operand
Op Code
Op Code of Next Instruction
Op Code
Op Code of Next
Op Code
Address of Next Instruction
Order Byte)
Address of Next
Order Byte)
Mode – ~~~~d~xed
Ut;;:~@&T A IN
Irrelevant
Irrelevant
Irrelevant
Irrelevant
Irrelevant
Irrelevant
Irrelevant
Irrelevant
Irrelevant
numerical valuq~’~~~@-by-cycle
,.‘.~’\\..!
:
(RTS) are used.
~, *.\:)fJ~
.+:Y>
.-,~. ‘‘\,.
Data from Stack
~
Data (Note 1 )
Data (Note 1 )
Data (Note 1 )
Data (Note 1 )
Data (Note 1 )
Data
Data
Data (Note 2)
Data (Note
Data Bus
Data
Data
~, \ .!-, s. ,,i,
INDEXED LOCATION
Comment
.}:\A ,#‘
Instruction
Instruction
Instruction
-!l!,., ,,
1 )
on the current
addressing,
is satisfied
(High
(Low
execution
(JSR),
A in