MC6800 Motorola, MC6800 Datasheet - Page 9

• Manufacturer Part Number: MC6800
• Description: 8-BIT MICROPROCESSING UNIT (MPU)
• Manufacturer: Motorola

while ~
necessary to delay program
be serviced. Interrupts will be latched internally while HALT
is low.
the chip; however, a 3 kQ external resistor to VCC should be
used for wire-OR and optimum
(WAI) – The MCWCO is capable of handling two types of in-
terrupts:
maskable (~)
maskable by the interrupt mask in the condition code register
by the M PU is the same except that each has its own vector
address. The behavior
shown in Figure 9 which details the MPU response to an in-
terruDt while the MPU is executina the control ~roaram. The
interrupt shown could be either ~Q or ~
chronous with respect to +2. The interrupt is shown going
low at time tpcs
an instruction
ecuted
Code Register (CCR) are pushed onto the stack,
The address of the interrupt service routine is then fetched
fram FFFC. FFFD for an NMI interruDt and from FFF8, FFF9
for an ~’interrupt.
vice routine, the execution of RTI will pull the PC, IX, ACCX,
and CCR off the stack; the Interrupt Mask bit is restored to
its condition
case, a WAIT instruction
for the interrupt.
response to the interrupt because the stacking of
ACCX,
waiting
dicating the following states of the control lj~~Y~MA
and the Address Bus, R/~and
impedance state. After the interrupt w-$*
previously described.
OR and optimum
Three-State
VMA and BA are forced low when TSC= “1”
false reads or writes on any device enabled by VMA.
high. This is done by insuring that no transitions of 41 (or 42)
occur during this period. (Logic levels of the clacks are irrele-
vant so long as they do not change).
dynamic device, the 01 clock can be stopped for a maximum
Register (IX), Accumulators
Bus and the Rim line are placed in a high-impedance
The HALT line must be in the high state for interrupts to
The ~
Non-Maskable
The Interrupt Mask bit is set to prevent further interrupts.
A 3-10 kQ external resistor to V&*’&~&tild be used for wire-
Three-State Control (TSC) – When the level sensitive
Figure 11 is a similar interrupt
‘$,~aip” ~
E&.~\x}i, , $ FFFB
FFFE
FFFQ”J”
MS
and the CCR is already done. While t~~$fM@
but
for the interrupt,
MEMORY MAP.@R IMRRUPT VECTORS
maskable
Vetior
is not maskable. The handling of these interrupts
has a high-impedance
Control (TSC) line is a logic “l”,
prior to Interrupts (see Figure 10).
instead
:,* E=3
(OP code fetch). This instruction
%FFD
,,f*y
which is an edge sensitive input.
in cycle #1 which precedes the first cycle of
Interrupt
control of igi~r~w~t~.
,.., ;. ‘~’
This technique
(~)
~
:.$
@
Upon complet~on of the interrupt ser-
the
—
‘*, ,,$’
of the MPU when
has been executed in prepara$$~
as described
Program
,*+ $
Non-Maskable Interrupt
Bus Available
..,,. “$,’
(NMI)
..
execution
Software Interrupt
(ACCX),
Interrupt Request
MOTOROLA
control of interrupts.
Data B~~ ~~, ~{ in the high
Description
sequence, except in this
puilup device internal to
and Wait for Interrupt
Reset
speeds up the M&U’”~
,.\, .<
},it?~ , ,,::
Counter
Since the MPU is a
and the Condition
while TSC is held
earlier,
and ca~ be asyn-
wilP&@+{Q?~h in-
interrupted
IS serviced as
(PC),
the Address
tbe~~~$.W,
to prevent
and non-
is not ex-
IRQ is
is
state.
Index
low,
It is
is
iS
$’+
Semiconductor
9
‘~+,’tv:a,::
“’t~, Available (BA) provides an indication
+..~.g@ the MPU will execute the instructions;
“*~PU will go to a halted or idle mode. A response signal, Bus
the MPU will go to locations FFFE and FFFF for the address
of the reset routine.
time PW@H without
90 pF may be d~&ly
{W,gf”Program execution by
status. When BA is low, the MPU is in the process of ex-
ecuting the control program;
the MPU from the system bus. VMA is forced low so that the
floating system bus will not activate any device on the bus
that is enabled by VMA.
and if either an ~
of the halted mode. If a RESET command occurs while the
state), and the Address Bus will contain address FFFE as
long as RESET is low, As soon as the RESET line goes high,
halting the MPU. The instruction
cycle instruction
struction.
the trailing edge of @l of the last cycle of an instruction
than the minmum tpcs
the instruction.
went low during 42 of that cycle, the
halted after completion
go high by time tBA (bus available delay time) after the last
instruction cycle.
Address Bus, and the Data Bus are in the high-impedance
state.
then can be used in a short Direct Memory Access (DMA)
application.
have its transitions at tTSE (three-state enable) while holding
+1 high and +2 low as shown, The Address Bus and Rl~
line will reach the high-impedance
delay), with VMA being forced low. In this exampl$~%the
Data Bus is also in the high-impedance
ing held low since DBE= 42. At this point in ti@e~,$,’)~MA
transfer could occur on cycles #3 and #4. -+$~SC
returned low, the MPU Address and R/~lfl&/&Mrn
bus. Because it is too late in cycle #5 to,,~cp~,~emory,
cycle is dead and used for synchroni$~~w.i$~rogram
tion resumes in cycle #6.
peripheral devices that the~@&.@~a~?d a ddress on the address
bus. In normal operation~<gti~, signal should be utilized for
enabling peripheral i~tf~f~w’
This signal is not thr@T~te.
all activik~~o?~~e machine will be halted. This input is level
sensitj,ve. +i.,,
halted and all internal activity has stopped,
line will be in a high-impedance
into the MPU and acted on as soon as the MPU is taken out
MPU is halted,
BA= low,
MPU will halt after completing
(point A of Figure 13). HALT must not go low any time later
Valid Memory Address (VM&,~~$ This output indicates to
l.ti~~
When BA is high, the Address Bus, Data Bus, and Rl~
While the MPU is halted, all program activity is stopped,
The fetch of the OP code by the M PU is the first cycle of
Figure 13 shows the timing relationships
Figure 12 shows the effect of TSC on the MPU. TSC must
HALT - ~h”~$’~%is level sensitive input is in the low state,
-.:<. ~.~~
The transition
Data Bus= high impedance,
..?XL?*
line provides an input
>’.~~’.
~, .,,+$s:
If HALT had not been low at Point A but
such as CLRA. When HALT goes low, the
At
the following
Products Inc.
or IRQ interrupt occurs, it will be latched
.:>
this point in time, VMA is low and R/~,
.y;.%,,a:.~+~b
destroying
dfiven by this active high signal.
of the following
specified.
of HALT must occur tpcs
~
an outside source. If HALT is
if BA is high, the MPU has
such as the PIA and ACiA.
One standard TTL load and
execution of the current in-
‘1~$ ~
data within the M PU. TSC
states occur:
state, effectively
illustrated is a one byte, 2
state at tTSD (three-state
.*’
.’~\k:\,
to
.:~:.3,
the MPU to allow
.!~:l
~.:~’
of the current MPU
state while,,~;~@&-
instruction.
..>;.
MPU would
Rl~=
involved when
if it is low, the
VMA= low,
high (read
removing
BA will
execu-
before
to the
have
con-
this
is