MC68HC11E Motorola, MC68HC11E Datasheet - Page 47

• Manufacturer Part Number: MC68HC11E
• Description: Microcontrollers
• Manufacturer: Motorola

2.3.3 System Initialization
M68HC11E Family — Rev. 5
MOTOROLA
SMOD = 0
SMOD = 1
Operating
Mode
Register
Address
$x03C
$x03D
$x03C
$x03D
$x024
$x035
$x039
$x024
$x035
$x039
Timer interrupt mask 2 (TMSK2)
Block protect register (BPROT)
System configuration options (OPTION)
Highest priority I-bit interrupt
and miscellaneous (HPRIO)
RAM and I/O map register (INIT)
Timer interrupt mask 2 (TMSK2)
Block protect register (BPROT)
System configuration options (OPTION)
Highest priority I-bit interrupt and
miscellaneous (HPRIO)
RAM and I/O map register (INIT)
IRV(NE) — Internal Read Visibility (Not E) Bit
PSEL[3:0] — Priority Select Bits
Registers and bits that control initialization and the basic operation of the MCU are
protected against writes except under special circumstances.
registers that can be written only once after reset or that must be written within the
first 64 cycles after reset.
IRVNE can be written once in any mode. In expanded modes, IRVNE
determines whether IRV is on or off. In special test mode, IRVNE is reset to 1.
In all other modes, IRVNE is reset to 0. For the MC68HC811E2, this bit is IRV
and only controls the internal read visibility function.
In single-chip modes this bit determines whether the E clock drives out from the
chip. For the MC68HC811E2, this bit has no meaning or effect in single-chip and
bootstrap modes.
Refer to
Special test
Single chip
Expanded
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
0 = E is driven out from the chip.
1 = E pin is driven low. Refer to the following table.
Bootstrap
Freescale Semiconductor, Inc.
Table 2-2. Write Access Limited Registers
Mode
Register Name
For More Information On This Product,
Section 5. Resets and
Operating Modes and On-Chip Memory
Go to: www.freescale.com
IRVNE Out
of Reset
0
0
0
1
E Clock Out
of Reset
Bits [1:0], once only
Clear bits, once only
Bits [5:4], bits [2:0], once only
See HPRIO description
Yes, once only
See HPRIO description
On
On
On
On
Interrupts.
in First 64 Cycles
Must be Written
of Reset
IRV Out
Operating Modes and On-Chip Memory
—
—
—
—
Off
Off
Off
On
Affects Only
IRVNE
IRV
IRV
Bits [7:2]
Set bits only
Bits [7:6], bit 3
See HPRIO description
All, set or clear
All, set or clear
All, set or clear
See HPRIO description
All, set or clear
E
E
Table 2-2
Anytime
Write
Memory Map
—
IRVNE Can
Be Written
lists
Data Sheet
Once
Once
Once
Once
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