UPD703014A NEC, UPD703014A Datasheet
UPD703014A
Related parts for UPD703014A
UPD703014A Summary of contents
Page 1
... KB ( PD703017A, 703017AY) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14526EJ2V0DS00 (2nd edition) ...
Page 2
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY APPLICATIONS { Low-power portable devices Cellular phones, PHSs, and camcorders ORDERING INFORMATION Part Number PD703014AGC- -8EU 100-pin plastic LQFP (fine-pitch) (14 PD703014AF1- -EA6 121-pin plastic FBGA (12 PD703014AYGC- -8EU 100-pin plastic LQFP (fine-pitch) (14 ...
Page 3
... P34/TO0/A13 14 P35/TO1/A14 15 P36/TI4/TO4/A15 16 P37/TI5/TO5 17 Note P100/RTP0/A5 19 P101/RTP1/A6 20 P102/RTP2/A7 21 P103/RTP3/A8 22 P104/RTP4/A9 23 P105/RTP5/A10 24 P106/RTP6/A11 25 Notes 1. Connect the IC pin directly Applies to the PD703014AY, 703015AY, and 703017AY only. 14 Data Sheet U14526EJ2V0DS00 75 P71/ANI1 74 P70/ANI0 73 AV REF P65/A21 69 P64/A20 68 P63/A19 67 P62/A18 ...
Page 4
... P70 B6 P05 C13 AV REF B7 P02 Note Connect the IC pin directly to V Remarks 1. Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic LQFP. 2. Connect the D4 pin directly PD703015AF1- -EA6 PD703015AYF1- -EA6 Bottom View ...
Page 5
... Ground for Bus Interface SS CLKOUT: Clock Output DSTB: Data Strobe HLDAK: Hold Acknowledge HLDRQ: Hold Request IC: Internally Connected INTP0 to INTP6: Interrupt Request From Peripherals LBEN: Lower Byte Enable NMI: Non-maskable Interrupt Request P00 to P07: Port 0 P10 to P15: Port 1 P20 to P27: Port 2 ...
Page 6
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY INTERNAL BLOCK DIAGRAM NMI INTC INTP0 to INTP6 Note 1 TI00, TI01, Timer/counters TI10, TI11 TO0, TO1 16-bit timer: TM0, TM1 TI2/TO2 TI3/TO3 8-bit timer: TI4/TO4 TM2 to TM5 TI5/TO5 SIO SO0 Note 3 ...
Page 7
... PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 1. PIN FUNCTIONS.................................................................................................................................. 8 1.1 Port Pins..................................................................................................................................................... 8 1.2 Non-Port Pins........................................................................................................................................... 11 1.3 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 14 2. ELECTRICAL SPECIFICATIONS...................................................................................................... 18 3. PACKAGE DRAWINGS..................................................................................................................... 42 4. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 44 CONTENTS Data Sheet U14526EJ2V0DS00 7 ...
Page 8
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 1. PIN FUNCTIONS 1.1 Port Pins Pin Name I/O PULL P00 I/O Yes Port 0 8-bit I/O port P01 Input/output can be specified in 1-bit units. P02 P03 P04 P05 P06 P07 P10 I/O ...
Page 9
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Pin Name I/O PULL P40 I/O No Port 4 8-bit I/O port P41 Input/output can be specified in 1-bit units. P42 P43 P44 P45 P46 P47 P50 I/O No Port 5 8-bit I/O port ...
Page 10
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Pin Name I/O PULL P90 I/O No Port 9 7-bit I/O port P91 Input/output can be specified in 1-bit units. P92 P93 P94 P95 P96 P100 I/O Yes Port 10 8-bit I/O port P101 ...
Page 11
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 1.2 Non-Port Pins Pin Name I/O PULL Output Yes Low-order address bus used for external memory expansion A5 to A12 A13 A14 A15 A16 to A21 Output No High-order address bus ...
Page 12
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Pin Name I/O PULL RTPTRG Input Yes RTP external trigger input R/W Output No External read/write status output RXD0 Input Yes Serial receive data input for UART0 and UART1 RXD1 SCK0 I/O Yes Serial ...
Page 13
... Low-order byte write strobe signal output for external data bus X1 Input No Resonator connection for main clock X2 XT1 Input No Resonator connection for subsystem clock XT2 IC Internally connected (connect directly to V Remark PULL: On-chip pull-up resistor Function ) SS Data Sheet U14526EJ2V0DS00 (3/3) Alternate Function P120 P92/R/W P90/LBEN ...
Page 14
... PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 1.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For the input/output schematic circuit diagram of each type, refer to Figure 1-1. Table 1-1. Types of Pin I/O Circuits (1/2) ...
Page 15
... P100 to RTP0/A5 to RTP7/A12 P107 P110 P113 P114 XT1 P120 WAIT AV REF CLKOUT RESET X2 XT2 IC I/O Circuit Type Recommended Connection of Unused Pins 5 Input: Connect Output: Leave open 26 Input: Connect Output: Leave open 5 Input: Connect Output: Leave open ...
Page 16
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Figure 1-1. Pin Input/Output Circuits (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Push-pull output that can be set for high-impedance output (both P-ch ...
Page 17
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Figure 1-1. Pin Input/Output Circuits (2/2) Type 10-A Pullup enable V DD Data P-ch Open drain N-ch Output disable Type 16 Feedback cut-off P-ch XT1 XT2 Type Pullup P-ch enable Data ...
Page 18
... Ports 7, 8, and their alternate-function pins sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other ...
Page 19
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge ...
Page 20
... Do not route the wiring near broken lines. 3. Sufficiently evaluate the matching between the oscillator and resonator. (b) External clock input Cautions 1. Connect the high-speed CMOS inverter as close as possible to the X1 pin. 2. Sufficiently evaluate the matching between the PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY and the high-speed CMOS inverter. ...
Page 21
... Sufficiently evaluate the matching between the oscillator and resonator. (b) External clock input XT1 Cautions 1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin. 2. Sufficiently evaluate the matching between the PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY and the high-speed CMOS inverter. ...
Page 22
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY DC Characteristics (1) Operating conditions (T = –40 to +85° Parameter Symbol Input voltage, high V Pins other than below IH1 V Note 1 IH2 Note 2 V IH3 V X1, XT1 ...
Page 23
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY (1) Operating conditions (T = –40 to +85° Parameter Symbol Note 5 Supply current I Subsystem clock normal operation mode DD5 f stopped) I Subsystem clock IDLE mode DD6 f stopped, watch ...
Page 24
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY (2) Operating conditions (T = –40 to +85° Parameter Symbol Input voltage, high V Pins other than below IH1 Note 1 V IH2 V Note 2 IH3 V X1, XT1 (P114), XT2 ...
Page 25
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY (2) Operating conditions (T = –40 to +85° Parameter Symbol Note 5 Supply current I Subsystem clock normal operation mode DD5 f stopped) I Subsystem clock IDLE mode DD6 f stopped, watch ...
Page 26
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Data Retention Characteristics (T = –40 to +85°C) A Parameter Symbol Data retention voltage V Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) ...
Page 27
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY AC Characteristics AC Test Input Waveforms (1) P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, and their alternate-function pins V DD 0. (2) P70 to ...
Page 28
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Load conditions Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device less by inserting a buffer or by some ...
Page 29
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Clock Timing (1) Operating conditions (T = –40 to +85° capacitance pF) L Parameter X1 input cycle XT1 input cycle X1 input high-level width XT1 input high-level width X1 ...
Page 30
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Clock Timing X1, XT1 (input) CLKOUT (output) (1) Timing of pins other than CLKOUT, ports and – 2.7 to 3.6 V, ...
Page 31
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Bus Timing (CLKOUT Asynchronous –40 to +85° 2 Parameter Address setup time (to ASTB ) Address hold time (from ASTB ) ...
Page 32
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Bus Timing (CLKOUT Synchronous –40 to +85° 2 Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address ...
Page 33
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait) T1 CLKOUT (output) <41> A16 to A21 (output A15 (output), Note AD0 to AD15 (I/O) <13> ASTB (output) <24> DSTB (output), RD (output) WAIT (input) Note ...
Page 34
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait) T1 CLKOUT (output) <41> A16 to A21 (output A15 (output), Note AD0 to AD15 (I/O) <43> <13> ASTB (output) <24> DSTB (output), WRL (output), WRH (output) ...
Page 35
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Bus Hold CLKOUT (output) <50> <51> HLDRQ (input) HLDAK (output) A16 to A19 (output), Note A1 to A15 (output) AD0 to AD15 (I/O) ASTB (output) DSTB (output), RD (output), WRL (output), WRH (output) Remark ...
Page 36
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Reset/Interrupt Timing (T = –40 to +85° 2 Parameter RESET high-level width RESET low-level width NMI high-level width NMI low-level width INTPn high-level ...
Page 37
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY TIn Input Timing (T = –40 to +85° 2 Parameter TIn0, TIn1 high-level width TIn high-level width TIn0, TIn1 low-level width TIn low-level ...
Page 38
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY CSI Timing (1) Master mode (T = –40 to +85° pF) L Parameter SCKn cycle time SCKn high-/low-level width SIn setup time (to SCKn ) SIn hold time (from ...
Page 39
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY UART Timing (T = –40 to +85° pF) L Parameter ASCKn cycle time t ASCKn high-level width ASCKn low-level width Remark ASCKn (input) Remark ...
Page 40
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Bus Mode ( PD703014AY, 703015AY, 703017AY only –40 to +85° 2 Parameter Symbol SCL clock frequency f CLK Bus-free time (between ...
Page 41
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Bus Mode ( PD703014AY, 703015AY, 703017AY only) <73> <72> SCL (I/O) <78> <77> <71> SDA (I/O) <70> Start Stop condition condition A/D Converter (T = –40 to +85° capacitance: ...
Page 42
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 3. PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. ...
Page 43
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY 121-PIN PLASTIC FBGA (12x12) E INDEX MARK Data Sheet U14526EJ2V0DS00 ...
Page 44
... For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions ...
Page 45
PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY [MEMO] Data Sheet U14526EJ2V0DS00 45 ...
Page 46
... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
Page 47
... PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability ...
Page 48
... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...