UPD703031A NEC, UPD703031A Datasheet

no-image

UPD703031A

Manufacturer Part Number
UPD703031A
Description
V850/SB1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Manufacturer
NEC
Datasheet
Document No. U14734EJ1V0DS00 (1st edition)
Date Published April 2000 N CP(K)
Printed in Japan
{ Watchdog timer: 1 channel
DESCRIPTION
single-chip microcontrollers of the V850 Family
interfaces, A/D converter, DMA controller, and so on are integrated on a single chip.
and 703033AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
designing.
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 50 ns (@ internal 20 MHz operation)
{ General-purpose registers: 32 bits
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 128 KB ( PD703031A, 703031AY: mask ROM)
{ Interrupt/exception:
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
{ Watch timer: 1 channel
The
The PD70F3033A and 70F3033AY have flash memory in place of the internal mask ROM of the PD703033A
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY (V850/SB1) are 32-/16-bit
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
load/store instructions
RAM: 12 KB ( PD703031A, 703031AY)
8-bit timer (6 channels: TM2 to TM7)
PD703031AY, 703033AY, 70F3033AY (external: 8, internal: 31 sources, exception: 1 source)
PD703031A, 703033A, 70F3033A (external: 8, internal: 30 sources, exception: 1 source)
256 KB ( PD703033A, 703033AY: mask ROM)
256 KB ( PD70F3033A, 70F3033AY: flash memory)
16 KB ( PD703033A, 703033AY, 70F3033A, 70F3033AY)
V850/SB1, V850/SB2
V850 Family User’s Manual Architecture:
703033AY, 70F3033A, 70F3033AY
PD703031A, 703031AY, 703033A,
32 registers
DATA SHEET
V850/SB1
TM
for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial
TM
User’s Manual Hardware: U13850E
TM
MOS INTEGRATED CIRCUIT
U10243E
©
2000

Related parts for UPD703031A

UPD703031A Summary of contents

Page 1

... Watchdog timer: 1 channel The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14734EJ1V0DS00 (1st edition) ...

Page 2

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY { Serial interface Asynchronous serial interface (UART0, UART1) Clocked serial interface (CSI0 to CSI3) 3-wire variable length serial interface (CSI4 bus interface (I C0, I C1) ( PD703031AY, 703033AY, ...

Page 3

... P100/RTP0/KR0/A5 20 P101/RTP1/KR1/A6 21 P102/RTP2/KR2/A7 22 P103/RTP3/KR3/A8 23 P104/RTP4/KR4/A9 24 P105/RTP5/KR5/A10 25 P106/RTP6/KR6/A11 Notes 1. IC: Connect directly Connect SCL0, SCL1, SDA0, and SDA1 are available only in the PD703031AY, 703033AY, and 70F3033AY. 14) PD70F3033AGC-8EU PD70F3033AYGC-8EU ( PD703031A, 703031AY, 703033A, 703033AY normal operation mode ( PD70F3033A, 70F3033AY). Data Sheet U14734EJ1V0DS00 ...

Page 4

... P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 Note 1 IC/V PP P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1 Notes 1. IC: Connect directly Connect SCL0, SCL1, SDA0, and SDA1 are available only in the PD703031AY, 703033AY, and 70F3033AY. 4 PD70F3033AGF-3BA PD70F3033AYGF-3BA ...

Page 5

... EV : Power Supply for Port Ground for Port SS HLDAK: Hold Acknowledge HLDRQ: Hold Request IC: Internally Connected INTP0 to INTP6: Interrupt Request from Peripherals KR0 to KR7: Key Return LBEN: Lower Byte Enable NMI: Non-Maskable Interrupt Request P00 to P07: Port 0 P10 to P15: Port 1 P20 to P27: ...

Page 6

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY INTERNAL BLOCK DIAGRAM NMI INTC INTP0 to INTP6 TI00, TI01, Timer/counters TI10, TI11 TO0, TO1 16-bit timer : TM0, TM1 TI2/TO2 8-bit timer TI3/TO3 : TM2 to TM7 TI4/TO4 TI5/TO5 SIO SO0 2 Note ...

Page 7

... Differences of PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY................. 8 2. PIN FUNCTIONS.................................................................................................................................. 9 2.1 Port Pins..................................................................................................................................................... 9 2.2 Non-Port Pins........................................................................................................................................... 11 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 15 3. PROGRAMMING FLASH MEMORY ( PD70F3033A, 70F3033AY ONLY) ................................... 19 3.1 Selecting Communication Mode ............................................................................................................ 19 3.2 Function of Flash Memory Programming.............................................................................................. 20 3.3 Connecting Dedicated Flash Programmer ............................................................................................ 20 4. ...

Page 8

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 1. DIFFERENCES AMONG PRODUCTS 1.1 Differences of PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY Part Number PD703031A Item Internal ROM 128 KB (mask ROM) Flash memory None programming pin Flash memory None programming mode ...

Page 9

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 2. PIN FUNCTIONS 2.1 Port Pins Pin Name I/O PULL P00 I/O Yes Port 0 8-bit I/O port P01 Input/output can be specified in 1-bit units. P02 P03 P04 P05 P06 P07 P10 I/O ...

Page 10

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Pin Name I/O PULL P60 to P65 I/O No Port 6 6-bit I/O port Input/output can be specified in 1-bit units. P70 to P77 Input No Port 7 8-bit input port P80 to P83 ...

Page 11

... Ground potential for I/O ports and alternate-function pins SS (except bus interface alternate port) HLDAK Output No Bus hold acknowledge output HLDRQ Input No Bus hold request input IC Internally connected ( PD703031A, 703031AY, 703033A, 703033AY only) Remark PULL: On-chip pull-up resistor Function Data Sheet U14734EJ1V0DS00 (1/4) Alternate Function P110/WAIT P111 P112 P113 ...

Page 12

... Output No External data bus’s low-order byte enable output NMI Input Yes Non-maskable interrupt request input RD Output No Read strobe output REGC Regulator output stabilization capacitance connection RESET Input System reset input RTP0 Output Yes Real-time output port RTP1 RTP2 RTP3 RTP4 ...

Page 13

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Pin Name I/O PULL I/O Yes Serial clock I/O for I SCL0 ( PD703031AY, 703033AY, 70F3033AY only) SCL1 SDA0 I/O Yes Serial transmit/receive data I/O for I ( PD703031AY, 703033AY, 70F3033AY only) SDA1 SI0 ...

Page 14

... Pin Name I/O PULL WRL Output No Low-order byte write strobe signal output for external data bus X1 Input No Resonator connection for main clock X2 XT1 Input No Resonator connection for subsystem clock XT2 Remark PULL: On-chip pull-up resistor 14 Function Data Sheet U14734EJ1V0DS00 (4/4) Alternate Function P90/LBEN ...

Page 15

... PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are show in Table 2-1. For the input/output schematic circuit diagram of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits (1/2) ...

Page 16

... Recommended Connection of Unused Pins Power Supply AV Independently connect resistor Input state: Independently connect Output state: Leave open. EV Input state: Independently connect Output state: Leave open. EV Input state: Independently connect Output state: Leave open. BV Leave open – ...

Page 17

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Figure 2-1. Pin Input/Output Circuits (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Push-pull output that can be set for high-impedance output (both P-ch ...

Page 18

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Figure 2-1. Pin Input/Output Circuits (2/2) Type 10-A Pullup enable V DD Data P-ch Open drain N-ch Output disable Type 16 Feedback cut-off P-ch XT1 XT2 Caution V in the circuit diagrams can be ...

Page 19

... There are the following two methods for writing a program to the flash memory. (1) On-board programming Write a program to the flash memory using a dedicated flash programmer after the 70F3033AY have been mounted on the target board. Also mount a connector, etc. on the target board to communicate with the dedicated flash programmer. (2) Off-board programming Write a program using a dedicated adapter before the PD70F3033A and 70F3033AY have been mounted on the target board ...

Page 20

... Silicon signature Reset 3.3 Connecting Dedicated Flash Programmer The connection of the dedicated flash programmer and the PD70F3033A and 70F3033AY differs according to the communication mode. The connections for each communication mode are shown below. Figure 3-2. Connection of Dedicated Flash Programmer in CSI0 Mode Dedicated flash programmer ...

Page 21

... PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Figure 3-3. Connection of Dedicated Flash Programmer in CSI0 + HS Mode Dedicated flash programmer GND RESET SI SO SCK HS Figure 3-4. Connection of Dedicated Flash Programmer in UART0 Mode Dedicated flash programmer GND RESET RxD TxD Data Sheet U14734EJ1V0DS00 ...

Page 22

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25° Parameter Symbol Supply voltage Input voltage ...

Page 23

... PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict ...

Page 24

... PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Recommended Oscillator (1) Main system clock oscillator (T = –40 to +85°C) A (a) Connection of ceramic resonator or crystal resonator Parameter Symbol Oscillation frequency f XX Oscillation stabilization time – – Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS). ...

Page 25

... PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (2) Subsystem clock oscillator (T = –40 to +85°C) A (a) Connection of crystal resonator Parameter Symbol Oscillation frequency f XT Oscillation stabilization time – Cautions 1. Subsystem clock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited. 2. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance ...

Page 26

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY DC Characteristics (T = –40 to +85° 4 Parameter Symbol Input voltage, high V Note 1 IH1 Note 2 V IH2 V Note 3 IH3 V ...

Page 27

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY DC Characteristics (T = –40 to +85° 4 Parameter Symbol Supply current PD703031A, I DD1 PD703031AY, I DD2 PD703033A, I DD3 PD703033AY I DD4 I DD5 ...

Page 28

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Data Retention Characteristics (T = –40 to +85°C) A Parameter Symbol Data retention voltage V Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) ...

Page 29

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY AC Characteristics (T = –40 to +85° Test Input Waveform ( Input ...

Page 30

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (1) Clock timing ( –40 to +85° 4 Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time ...

Page 31

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (2) Output waveform (other than port 4, port 5, port 6, port 9, X1, and CLKOUT – 4 Parameter Symbol Output ...

Page 32

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (4) Bus timing (a) Clock asynchronous (T = –40 to +85° Parameter Address setup time (to ASTB ) Address hold time (from ASTB ) Address float from DSTB Data input setup time ...

Page 33

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (b) Clock asynchronous (T = – Parameter Address setup time (to ASTB ) <10> Address hold time (from ASTB ) <11> Address float from DSTB <12> Data input setup ...

Page 34

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (c) Clock synchronous (T = –40 to +85° Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT ...

Page 35

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <38> A15 (output) A16 to A21 (output) Note (output) AD0 to AD15 (I/O) ASTB (output) DSTB, RD (output) WAIT (input) Note R/W, UBEN, ...

Page 36

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output A15 (output) A16 to A21 (output) Note (output) AD0 to AD15 (I/O) ASTB (output) DSTB, WRL, WRH (output) WAIT (input) Note R/W, UBEN, ...

Page 37

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (g) Bus hold timing CLKOUT (output) < 47 > < 48 > HLDRQ (input) HLDAK (output) A16 to A19 (output) Note (output A15 (output) AD0 to AD15 (I/O) ASTB (output) DSTB, RD ...

Page 38

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (5) Interrupt timing (T = –40 to +85° 4 Parameter NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width Remarks ...

Page 39

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (6) RPU timing (T = –40 to +85° Parameter TIn0, TIn1 high-level width <55> TIn0, TIn1 low-level width <56> TIn high-level width <57> TIn low-level width <58> Note T can select ...

Page 40

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (7) Asynchronous serial interface (UART0, UART1) timing (T = –40 to +85° 4 Parameter ASCKn cycle time <59> ASCKn high-level width <60> ASCKn low-level width <61> ...

Page 41

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (8) 3-wire serial interface (CSI0 to CSI3) timing (a) Master mode (T = –40 to +85° Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn ...

Page 42

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY (9) 3-wire variable length serial interface (CSI4) timing (a) Master mode (T = – Parameter SCK4 cycle <68> SCK4 high-level width <69> SCK4 low-level width <70> SI4 setup time ...

Page 43

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY SCK4 (I/O) SI4 (input) SO4 (output) Remark The broken lines indicate high impedance. <68> <69> <70> <71> <72> Input data <73> Output data Data Sheet U14734EJ1V0DS00 43 ...

Page 44

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 2 (10 bus mode ( PD703031AY, 703033AY, 70F3033AY only –40 to +85° 4 Parameter Symbol SCLn clock frequency – Bus-free time (between ...

Page 45

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY <76> <77> SCLn (I/O) <82> <81> <75> SDAn (I/O) <74> Stop Start condition condition Remark A/D Converter Characteristics (T = –40 to +85° capacitance pF) ...

Page 46

... EV ) after the Conditions Stabilization capacitance (Connected to REGC pin) <85> ) when RESET = V DD REG input before the t period has elapsed following the DD DD REG ), data may be driven from the pins until the t DD period has elapsed following the input of supply voltage ...

Page 47

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 4.1 Flash Memory Programming Mode ( PD70F3033A, 70F3033AY only) Basic characteristics ( Parameter Symbol Operating frequency f X Power supply voltage V DD Write current I DDW I ...

Page 48

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 5. PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material ...

Page 49

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY 100-PIN PLASTIC QFP (14x20 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...

Page 50

... For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions (1/2) ...

Page 51

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Table 6-1. Surface Mounting Type Soldering Conditions (2/2) (3) PD703031AGF- -3BA: 100-pin plastic QFP (14 PD703031AYGF- -3BA: 100-pin plastic QFP (14 PD703033AGF- -3BA: 100-pin plastic QFP (14 PD703033AYGF- -3BA: 100-pin plastic QFP (14 PD70F3033AGF-3BA: ...

Page 52

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY [MEMO] 52 Data Sheet U14734EJ1V0DS00 ...

Page 53

PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY [MEMO] Data Sheet U14734EJ1V0DS00 53 ...

Page 54

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Page 55

... PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • ...

Page 56

... The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...

Related keywords