UPD703037A NEC, UPD703037A Datasheet

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UPD703037A

Manufacturer Part Number
UPD703037A
Description
V850/SB2TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Manufacturer
NEC
Datasheet

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Document No. U14894EJ1V0DS00 (1st edition)
Date Published August 2000 J CP(K)
Printed in Japan
{ Watchdog timer: 1 channel
{ IEBus controller: 1 channel
of the V850 Family
DMA controller, and so on are integrated on a single chip.
and 703037AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
capacity are also available.
designing.
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)
{ General-purpose registers: 32 bits
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 512 KB ( PD703037A, 703037AY: mask ROM)
{ Interrupt/exception:
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
{ Watch timer: 1 channel
The PD703037A, 703037AY, 70F3037A, and 70F3037AY (V850/SB2) are 32-/16-bit single-chip microcontrollers
The PD70F3037A and 70F3037AY have flash memory in place of the internal mask ROM of the PD703037A
The
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
PD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY with different ROM/RAM
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
load/store instructions
TM
8-bit timer (6 channels: TM2 to TM7)
RAM: 24 KB ( PD703037A, 703037AY, 70F3037A, 70F3037AY)
for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter,
PD703037A, 703037AY, 70F3037A, 70F3037AY
PD703037AY, 70F3037AY (external: 8, internal: 34 sources, exception: 1 source)
PD703037A, 70F3037A, (external: 8, internal: 33 sources, exception: 1 source)
512 KB ( PD70F3037A, 70F3037AY: flash memory)
V850/SB1
V850 Family User’s Manual Architecture:
TM
32 registers
, V850/SB2 User’s Manual Hardware: U13850E
DATA SHEET
V850/SB2
TM
MOS INTEGRATED CIRCUITS
U10243E
©
2000

Related parts for UPD703037A

UPD703037A Summary of contents

Page 1

... IEBus controller: 1 channel The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14894EJ1V0DS00 (1st edition) ...

Page 2

Serial interface Asynchronous serial interface (UART0, UART1) Clocked serial interface (CSI0 to CSI3) 3-wire variable length serial interface (CSI4 bus interface (I C0, I C1) ( PD703037AY, 70F3037AY only) { 10-bit resolution A/D converter: ...

Page 3

... P36/TI4/TO4/A15 P37/TI5/TO5 Note 1 IC/V PP P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9/IERX P105/RTP5/KR5/A10/IETX P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1 Notes 1. IC: Connect directly Connect SCL0, SCL1, SDA0, and SDA1 are available only in the PD703037AY, 70F3037AY. PD703037A, 703037AY, 70F3037A, 70F3037AY PD70F3037AGF-3BA PD70F3037AYGF-3BA ...

Page 4

... Power Supply for Port Ground for Port SS HLDAK: Hold Acknowledge HLDRQ: Hold Request IC: Internally Connected IERX: IEBus Receive Data IETX: IEBus Transmit Data INTP0 to INTP6: Interrupt Request from Peripherals KR0 to KR7: Key Return LBEN: Lower Byte Enable NMI: Non-Maskable Interrupt Request ...

Page 5

INTERNAL BLOCK DIAGRAM NMI INTC INTP0 to INTP6 TI00, TI01, Timer/counters TI10, TI11 TO0, TO1 16-bit timer : TM0, TM1 TI2/TO2 8-bit timer TI3/TO3 : TM2 to TM7 TI4/TO4 TI5/TO5 SIO SO0 2 Note 3 Note 3 CSI0/I C0 SI0/SDA0 ...

Page 6

... DIFFERENCES AMONG PRODUCTS................................................................................................7 2. PIN FUNCTIONS ..................................................................................................................................8 2.1 Port Pins .....................................................................................................................................................8 2.2 Non-Port Pins ...........................................................................................................................................10 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................................14 3. PROGRAMMING FLASH MEMORY ( PD70F3037A, 70F3037AY ONLY) ....................................18 3.1 Selecting Communication Mode.............................................................................................................18 3.2 Function of Flash Memory Programming ..............................................................................................19 3.3 Connecting Dedicated Flash Programmer.............................................................................................19 4. ELECTRICAL SPECIFICATIONS ......................................................................................................21 4.1 Flash Memory Programming Mode ( PD70F3037A, 70F3037AY only) ................................................46 5 ...

Page 7

DIFFERENCES AMONG PRODUCTS Part Number Internal Type PD703034A None Mask ROM PD703034AY Provided PD703035A None Mask ROM PD703035AY Provided PD70F3035A None Flash memory PD70F3035AY Provided PD703037A None Mask ROM PD703037AY Provided PD70F3037A None Flash memory PD70F3037AY ...

Page 8

PIN FUNCTIONS 2.1 Port Pins Pin Name I/O PULL P00 I/O Yes Port 0 8-bit I/O port P01 Input/output can be specified in 1-bit units. P02 P03 P04 P05 P06 P07 P10 I/O Yes Port 1 6-bit I/O port ...

Page 9

Pin Name I/O PULL P60 to P65 I/O No Port 6 6-bit I/O port Input/output can be specified in 1-bit units. P70 to P77 Input No Port 7 8-bit input port P80 to P83 Input No Port 8 4-bit input ...

Page 10

... Ground potential for I/O ports and alternate-function pins SS (except bus interface alternate port) HLDAK Output No Bus hold acknowledge output HLDRQ Input No Bus hold request input IC Internally connected ( PD703037A, 703037AY only) Remark PULL: On-chip pull-up resistor 10 PD703037A, 703037AY, 70F3037A, 70F3037AY Function Data Sheet U14894EJ1V0DS00 (1/4) Alternate Function P110/WAIT P111 ...

Page 11

... Output No External data bus’s low-order byte enable output NMI Input Yes Non-maskable interrupt request input RD Output No Read strobe output REGC Regulator output stabilization capacitance connection RESET Input System reset input RTP0 Output Yes Real-time output port RTP1 RTP2 RTP3 RTP4 ...

Page 12

Pin Name I/O PULL SCK0 I/O Yes Serial clock I/O (3-wire type) for CSI0 to CSI3 SCK1 SCK2 SCK3 SCK4 I/O Yes Serial clock I/O (3-wire type) for variable length CSI4 SCL0 I/O Yes Serial clock I/O for I ( ...

Page 13

... No Low-order byte write strobe signal output for external data bus X1 Input No Resonator connection for main clock X2 XT1 Input No Resonator connection for subsystem clock XT2 Remark PULL: On-chip pull-up resistor PD703037A, 703037AY, 70F3037A, 70F3037AY Function Data Sheet U14894EJ1V0DS00 (4/4) Alternate Function P110/A1 P92/R/W ...

Page 14

... Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are show in Table 2-1. For the input/output schematic circuit diagram of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) Pin ...

Page 15

... Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2) Pin Alternate Function I/O Circuit Type P70 to ANI0 to ANI7 9 P77 P80 to ANI8 to ANI11 9 P83 P90 LBEN/WRL 5 P91 UBEN P92 R/W/WRH P93 DSTB/RD P94 ASTB P95 HLDAK 26 P96 HLDRQ 10-A P100 RTP0/A5/KR0 P101 RTP1/A6/KR1 ...

Page 16

Figure 2-1. Pin Input/Output Circuits (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Push-pull output that can be set for high-impedance output (both P-ch and N-ch off) Type 5 V ...

Page 17

Figure 2-1. Pin Input/Output Circuits (2/2) Type 10-A Pullup enable V DD Data P-ch Open drain N-ch Output disable Type 16 Feedback cut-off P-ch XT1 XT2 Caution V in the circuit diagrams can be read PD703037A, 703037AY, ...

Page 18

... There are the following two methods for writing a program to the flash memory. (1) On-board programming Write a program to the flash memory using a dedicated flash programmer after the 70F3037AY have been mounted on the target board. Also mount a connector, etc. on the target board to communicate with the dedicated flash programmer. (2) Off-board programming Write a program using a dedicated adapter before the PD70F3037A and 70F3037AY have been mounted on the target board ...

Page 19

... Silicon signature Reset 3.3 Connecting Dedicated Flash Programmer The connection of the dedicated flash programmer and the PD70F3037A or 70F3037AY differs according to the communication mode. The connections for each communication mode are shown below. Figure 3-2. Connection of Dedicated Flash Programmer in CSI0 Mode Dedicated flash programmer ...

Page 20

... Figure 3-3. Connection of Dedicated Flash Programmer in CSI0 + HS Mode Dedicated flash programmer Figure 3-4. Connection of Dedicated Flash Programmer in UART0 Mode Dedicated flash programmer 20 PD703037A, 703037AY, 70F3037A, 70F3037AY PD70F3037A, 70F3037AY GND V SS RESET RESET SI SO0 SO SI0 SCK SCK0 HS P15 PD70F3037A, 70F3037AY ...

Page 21

ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings ( ° Parameter Symbol Supply voltage Input voltage Analog input ...

Page 22

... Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict ...

Page 23

... Recommended Oscillator (1) Main system clock oscillator (T = –40 to +85 °C) A (a) Connection of ceramic resonator or crystal resonator Parameter Symbol Oscillation frequency f XX Oscillation stabilization time – – Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS). Cautions 1. Main system clock oscillator operates on the output voltage of the on-chip regulator. ...

Page 24

... Subsystem clock oscillator (T = –40 to +85 °C) A (a) Connection of crystal resonator Parameter Symbol Oscillation frequency f XT Oscillation stabilization time – Cautions 1. Subsystem clock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited. 2. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance ...

Page 25

DC Characteristics (T = –40 to +85 ° 4 Parameter Symbol Input voltage, high V Note 1 IH1 V Note 2 IH2 V Note 3 IH3 V Note 4 IH4 Input voltage, ...

Page 26

DC Characteristics (T = –40 to +85 ° 4 Parameter Symbol Supply current PD703037A, I DD1 PD703037AY I DD2 I DD3 I DD4 I DD5 I DD6 PD70F3037A, I DD1 PD70F3037AY I ...

Page 27

Data Retention Characteristics (T = –40 to +85 °C) A Parameter Symbol Data retention voltage V Data retention current I DDDR Supply voltage rise time t Supply voltage fall time t Supply voltage hold time t (from STOP mode setting) ...

Page 28

AC Characteristics (T = –40 to +85 ° test input waveform ( Input signal ...

Page 29

Clock timing ( –40 to +85 ° 4 Parameter CLKOUT output cycle <1> CLKOUT high-level width <2> CLKOUT low-level width <3> CLKOUT rise time <4> CLKOUT ...

Page 30

Output waveform (other than port 4, port 5, port 6, port 9, X1, and CLKOUT –40 to +85 ° 4 Parameter Symbol Output rise time <6> Output fall time ...

Page 31

Bus timing (a) Clock asynchronous (T = –40 to +85 ° Parameter Address setup time (to ASTB ) Address hold time (from ASTB ) Address float from DSTB Data input setup time from address Data input setup ...

Page 32

Clock asynchronous (T = –40 to +85 ° Parameter Address setup time (to ASTB ) Address hold time (from ASTB ) Address float from DSTB Data input setup time from address Data input setup time from DSTB ...

Page 33

Clock synchronous (T = –40 to +85 ° Parameter Delay time from CLKOUT to address <38> Delay time from CLKOUT to address <39> float Delay time from CLKOUT to ASTB <40> Delay time from CLKOUT to DSTB ...

Page 34

Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <38> A15 (output) A16 to A21 (output) Note (output) AD0 to AD15 (I/O) ASTB (output) DSTB, RD (output) WAIT (input) Note R/W, UBEN, LBEN Remark The broken lines indicate ...

Page 35

Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <38> A15 (output) A16 to A21 (output) Note (output) AD0 to AD15 (I/O) ASTB (output) DSTB, WRL, WRH (output) WAIT (input) Note R/W, UBEN, LBEN Remark The broken lines ...

Page 36

Bus hold timing CLKOUT (output) < 47 > < 48 > HLDRQ (input) HLDAK (output) A16 to A19 (output) Note (output A15 (output) AD0 to AD15 (I/O) ASTB (output) DSTB, RD (output) WRL, WRH (output) Note R/W, ...

Page 37

Interrupt timing (T = –40 to +85 ° 4 Parameter NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width Remarks Tsmp: Noise elimination ...

Page 38

RPU timing (T = –40 to +85 ° Parameter TIn0, TIn1 high-level width <55> TIn0, TIn1 low-level width <56> TIm high-level width <57> TIm low-level width <58> Note T (count clock cycle) can select the following ...

Page 39

Asynchronous serial interface (UART0, UART1) timing (T = –40 to +85 ° 4 Parameter ASCKn cycle time <59> ASCKn high-level width <60> ASCKn low-level width <61> Remark ...

Page 40

CSI3) timing (a) Master mode (T = –40 to +85 ° Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ) ...

Page 41

Master mode (T = –40 to +85 ° Parameter SCK4 cycle <68> SCK4 high-level width <69> SCK4 low-level width <70> SI4 setup time (to SCK4 ) <71> SI4 ...

Page 42

SCK4 (I/O) SI4 (input) SO4 (output) Remark The broken lines indicate high impedance. 42 PD703037A, 703037AY, 70F3037A, 70F3037AY <68> <69> <70> <71> <72> Input data <73> Output data Data Sheet U14894EJ1V0DS00 ...

Page 43

I C bus mode ( PD703037AY, 70F3037AY only –40 to +85 ° 4 Parameter Symbol SCLn clock frequency – Bus-free time (between <74> stop/start conditions) Note 1 Hold ...

Page 44

I C bus mode ( PD703037AY, 70F3037AY only –40 to +85 ° 4 <76> <77> SCLn (I/O) <82> <81> <75> SDAn (I/O) <74> Stop Start condition condition Remark ...

Page 45

... PD703037A, 703037AY, 70F3037A, 70F3037AY = 4 Conditions MIN. Communication mode: fixed to mode Conditions Stabilization capacitance (Connected to REGC pin) <85> ) when RESET = V DD REG input before the t period has elapsed following the DD DD REG ), data may be driven from the pins until the t ...

Page 46

Flash Memory Programming Mode ( PD70F3037A, 70F3037AY only) Basic Characteristics ( °C) A Parameter Symbol Operating frequency f X Power supply voltage V DD Write current I DDW I PPW Erase current I DDE I ...

Page 47

PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20 100 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. PD703037A, 703037AY, 70F3037A, 70F3037AY ...

Page 48

... The PD703037A, 703037AY, 70F3037A, and 70F3037AY should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions (1/2) PD703037AGF- ...

Page 49

Table 6-1. Surface Mounting Type Soldering Conditions (2/2) PD70F3037AGF-3BA: 100-pin plastic QFP (14 PD70F3037AYGF-3BA: 100-pin plastic QFP (14 Soldering Method Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds MAX. (at 210 °C or higher), Count: Two times or ...

Page 50

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Page 51

... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • Ordering information • ...

Page 52

... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...

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