UPD703100A-33 NEC, UPD703100A-33 Datasheet
UPD703100A-33
Related parts for UPD703100A-33
UPD703100A-33 Summary of contents
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... Industrial equipment: motor controllers, NC machine tools, etc. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 ORDERING INFORMATION Part Number PD703100AF1-33-FA1 157-pin plastic FBGA (14 PD703100AF1-40-FA1 157-pin plastic FBGA (14 PD703100AGJ-33-8EU 144-pin plastic LQFP (fine pitch) (20 PD703100AGJ-40-8EU 144-pin plastic LQFP (fine pitch) (20 PD703101AF1-33- -FA1 157-pin plastic FBGA (14 PD703101AGJ-33- -8EU ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 PIN CONFIGURATION (Top view) 157-pin plastic FGBA (14 14 mm) • PD703100AF1-33-FA1 • PD703100AF1-40- FA1 • PD703101AF1-33- -FA1 • PD703102AF1-33- -FA1 Top View ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Pin No. Pin Name D1 TI10/P03 D2 INTP100/DMARQ0/P04 — D14 V SS D15 A21/P65 D16 A20/P64 E1 TO101/P01 E2 TCLR10/P02 E14 HV DD E15 A23/P67 E16 A22/P66 F1 INTP113/DMAAK3/P17 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 144-pin plastic LQFP (fine pitch) (20 • PD703100AGJ-33-8EU • PD703100AGJ-40-8EU • PD703101AGJ-33- -8EU • PD703102AGJ-33- -8EU INTP103/DMARQ3/P07 1 INTP102/DMARQ2/P06 2 INTP101/DMARQ1/P05 3 INTP100/DMARQ0/P04 4 TI10/P03 5 TCLR10/P02 6 TO101/P01 7 TO100/P00 INTP113/DMAAK3/P17 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 PIN IDENTIFICATION A0 to A23: Address Bus ADTRG: AD Trigger Input ANI0 to ANI7: Analog Input AV : Analog Power Supply Analog Reference Voltage REF AV : Analog Ground SS BCYST: Bus Cycle ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 INTERNAL BLOCK DIAGRAM NMI INTP100 to INTP103, INTC INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153 TO100, TO101, TO110, TO111, TO120, TO121, TO130, TO131, RPU TO140, TO141, TO150, TO151 ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 1. DIFFERENCES AMONG PRODUCTS...........................................................................................10 2. PIN FUNCTIONS ............................................................................................................................11 2.1 Port Pins...............................................................................................................................11 2.2 Non-Port Pins.......................................................................................................................14 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ..................................18 3. FUNCTION BLOCKS .....................................................................................................................21 3.1 Internal Units........................................................................................................................21 ................................................................................................................................ 3.1.1 CPU 3.1.2 Bus control unit (BCU) .............................................................................................................................. 3.1.3 ROM ............................................................................................................................... 3.1.4 RAM .............................................................................................................................. 3.1.5 Ports 3.1.6 Interrupt controller (INTC) ....................................................................................................... 3.1.7 Clock generator (CG) 3.1.8 Real-time pulse unit (RPU) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 12. A/D CONVERTER ........................................................................................................................ 44 13. PORT FUNCTIONS ...................................................................................................................... 45 14. RESET FUNCTION ...................................................................................................................... 56 15. INSTRUCTION SET ..................................................................................................................... 57 16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES) .................................................... 67 17. PACKAGE DRAWING ............................................................................................................... 126 18. RECOMMENDED SOLDERING CONDITIONS......................................................................... ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 1. DIFFERENCES AMONG PRODUCTS Part Number PD703100 Item -33 -40 Internal ROM None Maximum operating 33 MHz 40 MHz frequency HV 4 Operation mode Single-chip None mode 0, 1 Flash memory None ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 2. PIN FUNCTIONS 2.1 Port Pins Pin Name I/O P00 I/O Port 0 8-bit I/O port P01 Input/output mode can be specified in 1-bit units P02 P03 P04 P05 P06 P07 P10 I/O Port 1 8-bit ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Pin Name I/O P50 to P57 I/O Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units P60 to P67 I/O Port 6 8-bit I/O port Input/output mode can be specified in 1-bit ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Pin Name I/O P120 I/O Port 12 8-bit I/O port P121 Input/output mode can be specified in 1-bit units P122 P123 P124 P125 P126 P127 PA0 I/O Port A 8-bit I/O port PA1 Input/output mode can ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 2.2 Non-Port Pins Pin Name I/O TO100 O Pulse signal output for timers TO101 TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TO150 TO151 TCLR10 I External clear signal input for timers 10 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Pin Name I/O INTP130 I External maskable interrupt request input, also used as external capture trigger input for timer 13 INTP131 INTP132 INTP133 INTP140 I External maskable interrupt request input, also used as external capture trigger ...
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... Input for specifying clock generator’s operation mode MODE0 to I Specify operation modes MODE3 RESET I System reset input X1 I Oscillator connection for system clock. Input is via X1 when using an external clock. X2 — ADTRG I A/D converter external trigger input AV I Reference voltage input for A/D converter ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Pin Name I/O CV — Positive power supply for dedicated clock generator DD CV — Ground potential for dedicated clock generator SS V — Positive power supply (power supply for internal units — Positive ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows the various circuit types using partially abridged diagrams. When connecting via a resistor, a resistance value in the range ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2) Pin I/O Circuit Type P92/RD 5 P93/WE P94/BCYST P95/OE P96/HLDAK P97/HLDRQ P100/TO120, P101/TO121 P102/TCLR12, P103/TI12 5-K P104/INTP120/TC0 to P107/INTP123/TC3 P110/TO140, P111/TOI41 5 P112/TCLR14, P113/TI14 5-K P114/INTP140 P115/INTP141/SO3 P116/INTP142/SI3 P117/INTP143/SCK3 P120/TO150, P121/TO151 5 P122/TCLR15, P123/TI15 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Type P-ch IN N-ch Type 2 IN Schmitt trigger input with hysteresis characteristics Type data P-ch output N-ch disable input enable Caution Replace V with HV when referencing the circuit ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 3. FUNCTION BLOCKS 3.1 Internal Units 3.1.1 CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, ...
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... A frequency of five times (using an on-chip PLL) or one-half times (not using an on-chip PLL) that of the input clock ( supplied as the internal system clock ( ). Either an external oscillator is connected to pins X1 and X2 XX (only when the on-chip PLL synthesizer is used external clock is input from the X1 pin as the input clock. ...
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... Programmable wait function for up to seven states for each memory block • External wait function using WAIT pin { Idle state insertion function { Bus mastering arbitration function { Bus hold function { Alternate function port pins are connectable to external bus 40-MHz operation) ... PD703100A- 33-MHz operation) ... PD703100A-33, 703101A-33, 703102A-33 Preliminary Data Sheet U14168EJ2V0DS00 23 ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 6. MEMORY ACCESS CONTROL FUNCTIONS 6.1 SRAM Connection The following figure shows an SRAM connection example. Figure 6-1. SRAM Connection Example A1 to A17 D15 CSn UWR LWR V850E/MS1 Remark A16 I/ ...
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... The page ROM controller can support page widths bytes. 6.2.1 Features { Can be connected directly to 8-bit or 16-bit page ROM { For 16-bit bus width, it supports 4-, 8-, 16-, or 32-word page access For 8-bit bus width, it supports 8-, 16-, 32-, or 64-word page access { Enables waits to be set ( waits) independently for off-page and on-page access 6 ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 6-2. Page ROM Connection Examples (2/ A20 CSn D8 to D15 V850E/MS1 Remark (b) 16-Mbit ( page ROM A0 to A19 WORD/BYTE 16-Mbit ( A19 WORD/BYTE 16-Mbit (2 M Preliminary Data Sheet U14168EJ2V0DS00 ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 6.3 DRAM Controller 6.3.1 Features { Generates the RAS, UCAS, and LCAS signals { Can be connected directly to high-speed page DRAM and EDO DRAM { Supports RAS hold mode { Can assign 4 types of DRAM to 8 memory block space { Supports 2CAS type DRAM { Can be switched between row and column address multiplex widths { Can insert waits ( waits) at each of the following timings • ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 6-3. DRAM Connection Examples (2/ A10 D15 RASn LCAS UCAS WE OE V850E/MS1 Remark (b) 4-Mbit ( DRAM I/O1 to I/O4 RAS CAS WE OE 4-Mbit ( DRAM I/O1 to I/O4 RAS CAS WE OE 4-Mbit ( DRAM ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 7. DMA FUNCTIONS (DMA CONTROLLER independent DMA channels { Transfer units bits { Maximum transfer count: 65536 ( Two types of transfer • Flyby (one-cycle) transfer • Two-cycle ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 7-1. DMA Function Block Diagram CPU TCn NMI INTPmn Request from on-chip peripheral I/O DMARQn DMAAKn External I/O Remark 15 Internal RAM Internal bus Internal ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 8. INTERRUPT/EXCEPTION PROCESSING FUNCTIONS 8.1 Features { Interrupts • Non-maskable interrupt: 1 source • Maskable interrupt: 47 sources • 8-level programmable priority control • Multiple interrupt control based on priority levels • Mask specification for each ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 8-1. Interrupt Control Function Block Diagram INTP100/INTCC100 INTP101/INTCC101 INTP102/INTCC102 INTP100 INTM1 INTP101 Note INTP103/INTCC103 INTP102 (edge detection) INTP103 INTP110/INTCC110 INTP111/INTCC111 INTP112/INTCC112 INTP110 INTM2 INTP111 Note INTP113/INTCC113 INTP112 (edge detection) INTP113 INTP120/INTCC120 INTP121/INTCC121 INTP122/INTCC122 RPU INTP120 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Interrupt/Exception Source Type Category Control Name Register Reset Interrupt RESET — Non- Interrupt NMI — maskable Note Software Exception TRAP0n — exception Note Exception TRAP1n — Exception Exception ILGOP — trap Maskable Interrupt INTOV10 OVIC10 Interrupt ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Interrupt/Exception Source Type Category Control Name Register Maskable Interrupt INTP123/ P12IC3 INTCC123 Interrupt INTP130/ P13IC0 INTCC130 Interrupt INTP131/ P13IC1 INTCC131 Interrupt INTP132/ P13IC2 INTCC132 Interrupt INTP133/ P13IC3 INTCC133 Interrupt INTP140/ P14IC0 INTCC140 Interrupt INTP141/ P14IC1 INTCC141 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Interrupt/Exception Source Type Category Control Name Register Maskable Interrupt INTSR0 SRIC0 Interrupt INTST0 STIC0 Interrupt INTCSI1 CSIC1 Interrupt INTSER1 SEIC1 Interrupt INTSR1 SRIC1 Interrupt INTST1 STIC1 Interrupt INTCSI2 CSIC2 Interrupt INTCSI3 CSIC3 Interrupt INTAD ADIC Remarks ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 9. CLOCK GENERATION FUNCTIONS { Multiplier function using a PLL (Phase locked loop) synthesizer { Clock sources • Oscillation by connecting an oscillator: f • External clock Power saving modes • HALT mode • IDLE mode • Software STOP mode • Clock output inhibit mode { Internal system clock output function Figure 9-1 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) { Measures the pulse interval and frequency, and outputs a programmable pulse • 16-bit measurements are possible • Can generate a variety of pulse patterns (interval pulse, one-shot pulse) { ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 10-1. Block Diagram of Timer 1 (16-bit Timer/Event Counter) TCLR10 Edge detection PRS100, PRM PRS101 101 TI10 Edge detection m 1/2 1/4 1/4 1/8 1/16 INTP100 Edge INTP101 Noise detection elimination INTP102 (INTM1) INTP103 TCLR11 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 10-2. Block Diagram of Timer 4 (16-bit Interval Timer) TM40 PRM400, PRM401 PRS400 1/2 1/16 Internal count clock m 1/4 1/8 1/32 TM41 Preliminary Data Sheet U14168EJ2V0DS00 Internal system TM40 (16 bits) Clear and start ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 11. SERIAL INTERFACE FUNCTION The serial interface function provides two 6-channel serial interfaces four channels can be used at the same time. (1) Asynchronous serial interface (UART0 and UART1): 2 channels (2) Clocked serial ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 11-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1) RXE0 Receive shift RXD0 register TXD0 Receive control parity check SCK0 1/16 RXD1 TXD1 SCK1 11.2 Clocked Serial Interfaces (CSI0 to ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 11-2. Block Diagram of Clocked Serial Interfaces (CSI0 to CSI3) CTXE0 SO0 CRXE0 Serial I/O shift register SI0 Serial clock control SCK0 circuit SO1 SI1 SCK1 SO2 SI2 SCK2 SO3 SI3 SCK3 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 11.3 Dedicated Baud Rate Generators (BRG0 to BRG2) { Serial clock can be selected via either dedicated baud rate generator output or internal system clock ( ) { Identical baud rates during transmission ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 12. A/D CONVERTER { Analog input: 8 channels { On-chip 10-bit A/D converter { On-chip A/D conversion result registers (ADCR0 to ADCR7) 10 bits 8 { A/D conversion trigger modes A/D trigger mode Timer trigger mode ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 13. PORT FUNCTIONS { Number of ports Dedicated input ports: 9 Input/output ports: 114 { Shares pins with other peripheral function I/O { Input and output can be specified in 1-bit units The block diagrams of ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-1. Block Diagram of Type A WR PMC PORT RD IN Remark m: port number n: bit number Figure 13-2. Block Diagram of Type B WR PMC PORT RD ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-3. Block Diagram of Type C WR PMC PMCmn WR PM PMmn Output signal in WR PORT control mode Pmn RD IN Remark mn: 24 (when mn = 24), 1 (when mn ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-5. Block Diagram of Type Output signal in WR PORT control mode RD IN Remark m: port number n: bit number Figure 13-6. Block Diagram of Type Output signal ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-7. Block Diagram of Type Input signal in control mode Remark Figure 13-8. Block Diagram of Type PMmn WR PORT Pmn RD IN Preliminary ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-9. Block Diagram of Type NMI Figure 13-10. Block Diagram of Type PORT RD IN Remark m: port number n: bit number 50 1 Noise elimination Address Edge ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-11. Block Diagram of Type K WR PCS PCSmn WR PMC PMCmn WR PM PMmn Output signal in WR PORT control mode Pmn RD IN Input signal in control mode Remark m: port number n: ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-12. Block Diagram of Type L WR PMC PORT RD IN Remark m: port number n: bit number 52 PMCmn PMmn Pmn Address Input signal in control mode Preliminary Data Sheet U14168EJ2V0DS00 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-13. Block Diagram of Type M WR PCS PCSmn WR PMC PORT RD IN INTP100 to INTP103, INTP132, INTP142 DMARQ0 to DMARQ3, SI2, SI3 Note When mn = 36: PCS35 When mn ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-14. Block Diagram of Type N WR PCS WR PMC WR PM Output signal in WR PORT control mode RD IN INTP133, INTP143 SCK2, SCK3 Remark mn: 37, 117 x: 2 (when mn = 37), ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Figure 13-15. Block Diagram of Type O WR PMC PMCmn WR PM PMmn Output signal in WR PORT control mode Pmn RD IN Remark m: port number n: bit number Figure 13-16. Block Diagram of Type ...
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... When the RESET input changes from low to high, the reset state is canceled and the CPU begins program execution (the contents of the various registers should be initialized within the program as necessary). An on-chip noise elimination circuit, which uses analog delay ( RESET pin. ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 15. INSTRUCTION SET Table 15-1. Symbols Used to Describe Operands Symbol reg1 General registers (r0 to r31): used as source registers reg2 General registers (r0 to r31): used mainly as destination registers reg3 General registers (r0 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Table 15-3. Symbols Used in Operation Symbol zero-extend (n) sign-extend (n) load-memory (a, b) store-memory ( load-memory-bit (a, b) store-memory-bit ( saturated (n) result Byte Half-word ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Table 15-5. Symbols Used in Flag Operations Identifier (Blank) No change 0 Clear to 0 Set or cleared according to the results R Previously saved values are restored Condition Condition Code Name (cond) (cccc) V 0000 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Instruction Set Mnemonic Operand Opcode ADD reg1,reg2 GR[reg2] GR[reg2]+GR[reg1] imm5,reg2 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Mnemonic Operand Opcode DISPOSE imm5,list12 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Mnemonic Operand Opcode LD.BU disp16[reg1],reg2 Notes ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Mnemonic Operand Opcode MULU reg1,reg2,reg3 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Mnemonic Operand Opcode SATADD reg1,reg2 GR[reg2] saturated(GR[reg2]+GR[reg1]) imm5,reg2 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Mnemonic Operand Opcode SST.H reg2,disp8[ep SST.W reg2,disp8[ep ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Mnemonic Operand Opcode XOR reg1,reg2 GR[reg2] GR[reg2] XOR GR[reg1] XORI imm16,reg1,reg2 ...
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... Storage temperature T Caution 1. Do not make direct connections of the output (or input/output) pins of the IC product with each other, and also avoid direct connections to V pins or the open collector pins can be directly connected with each other. A direct connection can also be made for an external circuit designed with timing specifications that prevent conflicting output from pins subject to high-impedance state ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Capacitance ( Parameter Symbol Input capacitance C Input/output capacitance C Output capacitance C Operating Conditions Operation Internal Operating Clock Frequency ( ) Mode Direct mode ...
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... CST5.00MGW040 CSA6.60MTZ CST6.60MTW CSA8.00MTZ CST8.00MTW Cautions 1. Connect the oscillation circuits as closely to the X1 and X2 pins as possible not wire any other signal lines in the area indicated by the broken line. 3. Thoroughly evaluate the matching between the PD703100A-33, 703100A-40, 703101-A33, 703102A-33 and the resonators. X1 ...
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... XX Kyocera PBRC5.00BR-A PBRC6.00BR-A PBRC6.60BR-A Cautions 1. Connect the oscillation circuits as closely to the X1 and X2 pins as possible not wire any other signal lines in the area indicated by the broken line. 3. Thoroughly evaluate the matching between the PD703100A-33, 703100A-40, 703101A-33, 703102A-33 and the resonators ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (b) External clock input (T = –40 to +70 C ... PD703100A-40 –40 to +85 C ... PD703100A-33, 703101A-33, 703102A-33) A Caution Input CMOS-level voltage to the X1 pin. Cautions when turning on/off ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 DC Characteristics (T = –40 to +70 C ... PD703100A-40 –40 to +85 C ... PD703100A-33, PD703101A-33, PD703102A-33 Parameter Symbol Input voltage, high V ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 DC Characteristics (T = –40 to +70 C ... PD703100A-40 –40 to +85 C ... PD703100A-33, PD703101A-33, PD703102A-33 Parameter Symbol Power supply During I ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Hold Characteristics(T = –40 to +70 C ... PD703100A-40 –40 to +85 C ... PD703100A-33, PD703101A-33, PD703102A-33) A Parameter Symbol Data hold voltage V DDDR Data hold current I DDDR Power supply ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 AC Characteristics (T = –40 to +70 C ... PD703100A-40 –40 to +85 C ... PD703100A-33, PD703101A-33, PD703102A-33 Test Input Waveform (a) P04/INTP100/DMARQ0 to ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Load Condition Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device's load capacitance lower. ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 <2> <4> X1 (PLL mode) <4> X1 (Direct mode) CLKOUT (output) <9> <7> Preliminary Data Sheet U14168EJ2V0DS00 <1> <3> <5> <1> <2> <3> <5> <10> <8> <6> 77 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (2) Output waveform (other than X1, CLKOUT) Parameter Output rise time <12> Output fall time <13> Signals other than X1, CLKOUT 78 Symbol Condition <12> Preliminary Data Sheet U14168EJ2V0DS00 MIN. MAX. Unit ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (3) Reset timing Parameter Symbol RESET high-level width <14> RESET low-level width <15> Remark T : Oscillation stabilization time OS RESET (input) Condition t WRSH t When power supply is on, and WRSL STOP mode has ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (4) SRAM, external ROM, external I/O access timing (a) Access timing (SRAM, external ROM, external I/O) (1/2) Parameter Address, CSn output delay time (from CLKOUT ) Address, CSn output hold time (from CLKOUT ) RD, IORD ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (a) Access timing (SRAM, external ROM, external I/O) (2/2) CLKOUT (Output A23 (Output) CSn (Output) BCYST (Output) RD, IORD (Output) [Read time] UWR, LWR, IOWR (Output) [Write time D15 (I/O) [Read time] ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (b) Read timing (SRAM, external ROM, external I/O) (1/2) Parameter Data input setup time (to address) Data input setup time (to RD) RD, IORD low-level width RD, IORD high-level width RD, IORD delay time from address, ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (b) Read timing (SRAM, external ROM, external I/O) (2/2) CLKOUT (Output A23 (Output) CSn (Output) UWR, LWR, IOWR (Output) RD, IORD (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. This is ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (c) Write timing (SRAM, external ROM, external I/O) (1/2) Parameter WAIT setup time (to address) WAIT setup time (to BCYST ) WAIT hold time (from BCYST ) UWR, LWR, IOWR delay time from address, CSn Address ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (c) Write timing (SRAM, external ROM, external I/O) (2/2) CLKOUT (Output A23 (Output) CSn (Output) RD, IORD (Output) UWR, LWR, IOWR (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. This is ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (d) DMA flyby transfer timing (SRAM Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) RD low-level width RD high-level width RD delay time from address, CSn Address delay time from RD ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (d) DMA flyby transfer timing (SRAM CLKOUT (Output A23 (Output) CSn (Output) RD (Output) UWR, LWR (Output) DMAAKm (Output) IORD (Output) IOWR (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. This ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (e) DMA flyby transfer timing (external I/O Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) IORD low-level width IORD high-level width IORD delay time from address, CSn Address delay time from ...
Page 89
PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (e) DMA flyby transfer timing (external I/O CLKOUT (Output A23 (Output) CSn (Output) UWR, LWR (Output) RD (Output) DMAAKm (Output) IOWR (Output) IORD (Output D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (5) Page ROM access timing (1/2) Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Off-page data input ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (5) Page ROM access timing (2/2) CLKOUT (Output) Note Off-page address CSn (Output) Note On-page address UWR, LWR (Output) RD (Output D15 (I/O) WAIT (Input) BCYST (Output) Note On-page and off-page addresses are as ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (6) DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3) Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3) Parameter RAS column address delay time RAS-CAS delay time Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3) TRPW CLKOUT (Output) <56> A23 (Output) <61> RASn (Output) <66> UCAS (Output) LCAS (Output) WE (Output) OE (Output D15 (I/O) WAIT ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 [MEMO] Preliminary Data Sheet U14168EJ2V0DS00 95 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (b) Read timing (high-speed page DRAM access: on-page) (1/2) Parameter Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time from OE Column address setup time Column address ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (b) Read timing (high-speed page DRAM access: on-page) (2/2) CLKOUT (Output A23 (Output) RASn (Output) UCAS (Output) LCAS (Output) WE (Output) OE (Output D15 (I/O) WAIT (Input) Remarks 1. This is the ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2) Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Row address setup time Row address hold time Column address setup time ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2) TRPW CLKOUT (Output) <56> A23 (Output) <61> RASn (Output) <66> UCAS (Output) LCAS (Output) OE (Output) WE (Output D15 (I/O) WAIT ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (d) Write timing (high-speed page DRAM access: on-page) (1/2) Parameter Column address setup time Column address hold time RAS hold time Column address read time (from RAS ) CAS pulse width CAS precharge time RAS hold ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (d) Write timing (high-speed page DRAM access: on-page) (2/2) CLKOUT (Output A23 (Output) RASn (Output) UCAS (Output) LCAS (Output) OE (Output) WE (Output) <90> D15 (I/O) WAIT (Input) Remarks 1. This is ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (e) Read timing (EDO DRAM) (1/3) Parameter Data input setup time (to CLKOUT ) Data input hold time (from CLKOUT ) Data output delay time from OE Row address setup time Row address hold time Column ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (e) Read timing (EDO DRAM) (2/3) Parameter Output enable access Off-page time On-page Remarks CYK the number of waits due to the RPCxx bit of the DRCn register (n ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (e) Read timing (EDO DRAM) (3/3) TRPW CLKOUT (Output) <56> A23 (Output) Row address <61> RASn (Output) <66> UCAS (Output) LCAS (Output) <68> WE (Output) OE (Output D15 (I/O) BCYST (Output) WAIT ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 [MEMO] Preliminary Data Sheet U14168EJ2V0DS00 105 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (f) Write timing (EDO DRAM) (1/2) Parameter Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time RAS hold time Column address read time (from RAS ) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (f) Write timing (EDO DRAM) (2/2) TRPW CLKOUT (Output) <56> A23 (Output) <61> RASn (Output) <66> UCAS (Output) LCAS (Output) RD (Output) OE (Output) WE (Output D15 (I/O) BCYST (Output) WAIT (Input) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) Data output delay time from OE IOWR delay time from address Address setup time ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Remarks CYK 2. w: the number of waits due to WAIT the number of waits due to the RPCxx bit of the DRCn register ( ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) Parameter Output buffer turn-off delay time (from OE ) Output buffer turn-off delay time (from CAS ) CAS precharge time High-speed page mode cycle time RAS hold ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) TRPW CLKOUT (Output A23 (Output) RASn (Output) UCAS (Output) LCAS (Output) RD (Output) OE (Output) DMAAKm (Output) WE (Output) IORD (Output) IOWR (Output ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (h) DMA flyby transfer timing (external I/O Parameter WAIT setup time (to CLKOUT ) WAIT hold time (from CLKOUT ) IORD low-level width IORD high-level width IORD delay time from address, CSn Address delay time from ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Remarks CYK 2. w: the number of waits due to WAIT the number of waits due to the RHCxx bit of the DRCn register ( ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (h) DMA flyby transfer timing (external I/O Parameter CAS delay time from DMAAKm CAS delay time from IORD IORD delay time from WE Remarks CYK 2. w: the number of waits due ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (h) DMA flyby transfer timing (external I/O T1 TRPW CLKOUT (Output) <56> A23 (Output) Row address <61> RASn (Output) <66> UCAS (Output) LCAS (Output) RD (Output) OE (Output) WE (Output) DMAAKm (Output) IOWR (Output) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (i) CBR refresh timing Parameter RAS precharge time RAS pulse width CAS hold time REFRQ pulse width RAS precharge CAS hold time REFRQ active delay time (from CLKOUT ) REFRQ inactive delay time (from CLKOUT ) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (j) CBR self-refresh timing Parameter REFRQ active delay time (from CLKOUT ) REFRQ inactive delay time (from CLKOUT ) CAS hold time RAS precharge time Remarks CYK the number ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (7) DMAC timing Parameter DMARQn setup time (to CLKOUT ) DMARQn hold time (from CLKOUT ) DMAAKn output delay time (from CLKOUT ) DMAAKn output hold time (from CLKOUT ) TCn output delay time (from CLKOUT ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 [MEMO] Preliminary Data Sheet U14168EJ2V0DS00 119 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (8) Bus hold timing (1/2) Parameter HLDRQ setup time (to CLKOUT ) HLDRQ hold time (from CLKOUT ) HLDAK delay time from CLKOUT HLDRQ high-level width HLDAK low-level width Bus float delay time from CLKOUT Bus ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (8) Bus hold timing (2/2) T1 CLKOUT (Output) <123> <124> HLDRQ (Intput) HLDAK (Output A23 (Output D15 (I/O) CSn/RASn (Output) BCYST (Output) RD (Output) WE (Output) UCAS (Output) LCAS (Output) WAIT (Input) ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (9) Interrupt timing Parameter NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width Remarks 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or ...
Page 123
PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (11) UART0, UART1 timing (clock-synchronized or master mode only) Parameter SCKn cycle SCKn high-level width SCKn low-level width RXDn setup time (to SCKn ) RXDn hold time (from SCKn ) TXDn output delay time (from SCKn ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 (12) CSI0 to CSI3 timing (a) Master mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn ) SIn hold time (from SCKn ) SOn output delay time (from SCKn ) ...
Page 125
PD703100A-33, 703100A-40, 703101A-33, 703102A-33 A/D Converter Characteristics (T = –40 to +70 C ... PD703100A-40 –40 to +85 C ... PD703100A-33, PD703101A-33, PD703102A-33 – 0 Parameter Symbol Resolution – ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 17. PACKAGE DRAWING 157-PIN PLASTIC FBGA (14x14 INDEX MARK 4-R0.3 4-C1 157- b 126 ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 144 PIN PLASTIC LQFP (FINE PITCH) (20 20) 108 109 144 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ...
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... This product should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Surface Mounting Type Soldering Conditions ...
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PD703100A-33, 703100A-40, 703101A-33, 703102A-33 [MEMO] Preliminary Data Sheet U14168EJ2V0DS00 129 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • ...
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... The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...