MT32LD3264A MICRON [Micron Technology], MT32LD3264A Datasheet - Page 14

• Manufacturer Part Number: MT32LD3264A
• Description: DRAM MODULE
• Manufacturer: MICRON [Micron Technology]

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10.If CAS# and RAS# = V
11.If CAS# = V
12.Measured with a load equivalent to two TTL gates
13.Requires that
14.Requires that
15.If CAS# is LOW at the falling edge of RAS#,
16.The
17.The
18.Either
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
rates. Specified values are obtained with minimum
cycle time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range is ensured.
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
for -6.
measuring timing of input signals. Transition times
are measured between V
and V
specification, all input signals must transit between
V
tonic manner.
the last valid READ cycle.
and 100pF and V
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
without the
must always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively
by
or without the
t
cycle.
REF refresh requirement is exceeded.
RCD was greater than the specified
RAD was greater than the specified
CAC must always be met.
CC
IH
IH
t
t
is dependent on output loading and cycle
(MIN) and V
and V
CAC (
AA (
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
IH
t
RCH or
).
t
RAC and
IL
t
RAC [MIN] no longer applied). With or
(or between V
IL
t
RCD (MAX) limit,
, data output may contain data from
t
t
AA and
AA and
t
t
RRH must be satisfied for a READ
RAD (MAX) limit,
IL
OL
(MAX) are reference levels for
t
CAC no longer applied). With
= 0.8V and V
IH
t
t
CAC are not violated.
RAC are not violated.
IH
, data output is High-Z.
IL
t
and V
T = 2ns for -5 and 2.5ns
SS
and V
DD
.
= +3.3V; f = 1 MHz.
t
IL
AA and
OH
IH
(or between V
t
) in a mono-
AA,
= 2V.
t
t
RCD (MAX)
RAD (MAX)
t
RAC and
t
CAC
t
CP.
t
t
RCD
RAD
IL
14
19.
20.A HIDDEN REFRESH may also be performed after
21.The maximum current ratings are based with the
22.These parameters are referenced to CAS# leading
23.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
26.Measured with the specified current load and
27.
28.The SPD EEPROM WRITE cycle time (
29.If OE# is tied permanently LOW, LATE WRITE or
30. V
t
achieves the open circuit condition and is not
referenced to V
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half when used in the x32
mode.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
t
operating parameters.
WRITE cycles. If
an EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle.
MODIFY-WRITE cycles. Meeting these limits
allows for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.
t
WRITE cycle.
design.
100pF.
t
latter of the RAS# and CAS# signals to transition
HIGH.
time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit are disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
READ-MODIFY-WRITE operations are not
possible.
width ≤ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
undershoot: V
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
OFF (MAX) defines the time at which the output
WCS,
CWD and
OFF on an EDO module is determined by the
NONBUFFERED DRAM DIMMs
IH
overshoot: V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
RWD,
RWD,
t
AWD are not applicable in a LATE
t
t
IL
AWD and
AWD and
OH
(MIN) = -2V for a pulse width ≤
t
IH
WCS >
or V
8, 16, 32 MEG x 64
(MAX) = V
OL
t
WCS applies to EARLY
.
t
t
t
WCS (MIN), the cycle is
CWD define READ-
CWD are not restrictive
DD
+ 2V for a pulse
©1999, Micron Technology, Inc.
t
t
WCS,
WR) is the
IL
t
RWD,