MT32LD3264A MICRON [Micron Technology], MT32LD3264A Datasheet - Page 6

• Manufacturer Part Number: MT32LD3264A
• Description: DRAM MODULE
• Manufacturer: MICRON [Micron Technology]

PIN DESCRIPTIONS
8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs
DM78.p65 – Rev. 2/99
55-58, 60, 65-67, 69-72,
6, 18, 26, 40, 41, 49, 59,
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
2-5, 7-11, 13-17, 19-20,
124, 133, 143, 157, 168
127, 138, 148, 152, 162
139-142, 144, 149-151,
125-126, 128, 132, 146
73, 84, 90, 102, 110,
74-77, 86-89,91-95,
28, 29, 46, 47, 112,
153-156, 158-161
97-101, 103-104,
42, 62, 111, 115,
PIN NUMBERS
30, 45, 114, 129
33-38, 117-122
113, 130, 131
165-167
27, 48
31, 44
82
83
RAS0#-RAS3#
CAS0#-CAS7#
WE0#, WE2#
OE0#, OE2#
DQ0-DQ63
SYMBOL
SA0-SA2
A0-A11
SDA
RFU
SCL
V
V
DD
SS
Input/Output Serial Presence-Detect Data. SDA is a bidirectional pin
Output
Supply
Supply
Input/
Input
Input
Input
Input
Input
Input
TYPE
Input
–
6
Row-Address Strobe: RAS# is used to clock-in the
row-address bits. Two RAS# inputs allow for one x64
bank or two x32 banks.
Column-Address Strobe: CAS# is used to clock-in the
column-address bits, enable the DRAM output
buffers and strobe the data inputs on WRITE cycles.
Eight CAS# inputs allow byte access control for any
memory bank configuration.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. WE0# controls DQ0-DQ31. WE2# controls
DQ32-DQ63. If WE# is LOW prior to CAS# going
LOW, the access is an EARLY WRITE cycle. If WE# is
HIGH while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
Output Enable: OE# is the input/output control for
the DQ pins. OE0# controls DQ0-DQ31. OE2# controls
DQ32-DQ63. These signals may be driven, allowing
LATE WRITE cycles.
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs
to the addressed DRAM location. BYTE WRITEs may
be performed by using the corresponding CAS#
select (x64 mode only). For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
Reserved for Future Use: These pins should be left
unconnected.
Power Supply: +3.3V ±0.3V.
Ground.
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs. These pins are used
to configure the presence-detect device.
NONBUFFERED DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
8, 16, 32 MEG x 64
©1999, Micron Technology, Inc.