MBM29F080A-55 FUJITSU [Fujitsu Component Limited.], MBM29F080A-55 Datasheet - Page 21

• Manufacturer Part Number: MBM29F080A-55
• Description: 8M (1M X 8) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

Data Protection
Low V
Write Pulse “Glitch” Protection
Logical Inhibit
Power-Up Write Inhibit
The MBM29F080A is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 3.2 V (typically 3.7 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the device with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
CC
CC
level is greater than V
Write Inhibit
LKO
CC
. It is the users responsibility to ensure that the control pins are logically correct
< V
LKO
, the command register is disabled and all internal program/erase circuits
CC
is above 3.2 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
IL
, CE = V
IH
will not accept commands on the rising edge of WE.
IH
or WE = V
MBM29F080A
IH
. To initiate a write cycle CE and WE
-55/-70/-90
CC
power-up
CC
less
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