MBM29F400BC-55 FUJITSU [Fujitsu Component Limited.], MBM29F400BC-55 Datasheet - Page 20

• Manufacturer Part Number: MBM29F400BC-55
• Description: 4M (512K X 8/256K X 16) BIT
• Manufacturer: FUJITSU [Fujitsu Component Limited.]

20
MBM29F400TC
RY/BY
Ready/Busy
RESET
Hardware Reset
Byte/Word Configuration
Data Protection
Furthermore, DQ
mode, DQ
The MBM29F400TC/BC provides a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands. If
the MBM29F400TC/BC is placed in an Erase Suspend mode, the RY/BY output will be high. Also, since this is
an open drain output, many RY/BY pins can be tied together in parallel with a pull up resistor to V
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing diagram.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to V
The MBM29F400TC/BC device may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
device requires time of t
standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset
occurs during a program or erase operation, the data at that particular location will be corrupted. Please note
that the RY/BY output signal should be ignored during the RESET pulse. Refer to Figure 12 for the timing diagram.
Refer to Temporary Sector Unprotection for additional functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29F400TC/BC device. When this
pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ
DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to Figures 13, 14 and 15 for the timing diagram.
The MBM29F400TC/BC are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporate several features to prevent inadvertent write cycles resulting form V
power-down transitions or system noise.
15
. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, the DQ
2
toggles if this bit is read from the erasing sector.
TM
2
Algorithms are either in progress or completed. If the output is low, the device is busy with
can also be used to determine which sector is being erased. When the device is in the erase
RH
before it will allow read access. When the RESET pin is low, the device will be in the
-55/-70/-90
IL
) for at least 500 ns in order to properly reset the internal state machine.
8
to DQ
/MBM29F400BC
14
bits are tri-stated. However, the command bus cycle is always
0
to DQ
7
and the DQ
IL
. The RESET pin has a pulse
8
to DQ
-55/-70/-90
15
bits are ignored. Refer
CC
power-up and
CC
.
15
/A
-1
pin
0
CC
to
.