CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet - Page 19

• Manufacturer Part Number: CY7C0851V
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document Number: 38-06070 Rev. *L
Notes
28. CE is internal signal. CE = LOW if CE
29. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
30. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
31. The output is disabled (high-impedance state) by CE = V
32. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
Numbers are for reference only.
MRST
ALL
ADDRESS/
DATA
LINES
ALL
OTHER
INPUTS
TMS
CNTINT
INT
TDO
ADDRESS
DATA
B0–B3
R/W
CLK
OUT
OE
CE
t
t
t
RSF
t
t
SB
SW
SA
SC
A
n
t
RS
t
t
t
t
HB
HW
HA
t
HC
CH2
0
1 Latency
= LOW and CE
t
INACTIVE
RSS
t
CYC2
t
RSR
t
CKLZ
t
CL2
1
Figure 9. Read Cycle
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
IH
A
following the next rising edge of the clock.
n+1
Figure 8. Master Reset
ACTIVE
t
CD2
IL
with CNT/MSK = V
[28, 29, 30, 31, 32]
Q
A
n
n+2
IH
constantly loads the address on the rising edge of the CLK.
t
DC
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Q
t
SC
n+1
t
OHZ
A
n+3
t
OLZ
t
HC
t
OE
Page 19 of 39
Q
n+2