CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet - Page 7

• Manufacturer Part Number: CY7C0851V
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Definitions
Notes
Document Number: 38-06070 Rev. *L
A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ
OE
INT
CNTINT
R/W
B
MRST
TMS
TDI
TCK
TDO
V
V
3. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits.
4. These pins are not available for CY7C0853V/CY7C0853AV device.
0L
0L
SS
DD
Left Port
L
0L
–A
L
–B
L
L
L
L
L
[4]
[4]
–DQ
[4]
17L
3L
L
L
[4]
L
[3]
[4]
[4]
L
35L
[4]
A
ADS
CE0
CE1
CLK
CNTEN
CNTRST
CNT/MSK
DQ
OE
INT
CNTINT
R/W
B
Right Port
0R
0R
R
0R
R
–A
–B
R
R
R
R
R
[4]
[4]
–DQ
[4]
17R
3R
R
R
[4]
R
[4]
[3]
R
[4]
35R
[4]
Address inputs.
Address strobe input. Used as an address qualifier. This signal should be asserted LOW for the part
using the externally supplied address on the address pins and for loading this address into the burst
address counter.
Active LOW chip enable input.
Active HIGH chip enable input.
Clock signal. Maximum clock input rate is f
Counter enable input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are asserted
LOW.
Counter reset input. Asserting this signal LOW resets to zero the unmasked portion of the burst
address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN.
Address counter mask register enable input. Asserting this signal LOW enables access to the
mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
Data bus input/output.
Output enable input. This asynchronous signal must be asserted LOW to enable the DQ data pins
during Read operations.
Mailbox interrupt flag output. The mailbox permits communications between ports. The upper two
memory locations can be used for message passing. INT
to the mailbox location of the left port, and vice versa. An interrupt to a port is deasserted HIGH when
it reads the contents of its mailbox.
Counter interrupt output. This pin is asserted LOW when the unmasked portion of the counter is
incremented to all “1s.”
Read/Write enable input. Assert this pin LOW to write to, or HIGH to Read from the dual port memory
array.
Byte select inputs. Asserting these signals enables Read and Write operations to the corresponding
bytes of the memory array.
Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting MRST
LOW performs all of the reset functions as described in the text. A MRST operation is required at
power up.
JTAG test mode select input. It controls the advance of JTAG TAP state machine. State machine
transitions occur on the rising edge of TCK.
JTAG test data input. Data on the TDI input is shifted serially into selected registers.
JTAG test clock input.
JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
Ground inputs.
Power inputs.
Description
MAX
.
L
is asserted LOW when the right port writes
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
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