CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet - Page 21

• Manufacturer Part Number: CY7C0851V
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document Number: 38-06070 Rev. *L
Notes
39. Addresses do not have to be accessed sequentially since ADS = CNTEN = V
40. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
41. CE
42. CE
ADDRESS
ADDRESS
DATA
Numbers are for reference only
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
DATA
CNTEN
DATA
0
0
= B0 – B3 = R/W = LOW; CE
= OE = B0 – B3 = LOW; CE
ADS
CLK
CLK
R/W
OUT
OUT
CE
OE
IN
t
t
t
SAD
SCN
SA
t
t
t
SW
SC
SA
Q
A
x–1
n
A
t
EXTERNAL
ADDRESS
n
CH2
t
READ
CH2
t
1
1
CYC2
t
t
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
t
HAD
HCN
= R/W = CNTRST = MRST = HIGH.
t
HA
t
CYC2
t
t
(continued)
HW
Figure 12. Read-to-Write-to-Read (OE Controlled)
HC
HA
t
CL2
t
CL2
Figure 13. Read with Address Counter Advance
Q
A
x
READ
t
n+1
DC
t
CD2
t
CD2
READ WITH COUNTER
Q
t
OHZ
n
t
SW
t
Q
SD
D
A
n
n+2
n+2
t
HW
t
HD
IL
with CNT/MSK = V
t
t
SAD
SCN
Q
WRITE
A
D
n+1
COUNTER HOLD
n+3
n+3
IH
constantly loads the address on the rising edge of the CLK.
t
t
HCN
HAD
[39, 40, 41, 42]
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
[41]
A
n+4
t
CD2
Q
READ WITH COUNTER
n+2
READ
Q
n+1
A
n+5
t
CD2
Page 21 of 39
Q
n+4
Q
n+3