AD7885 AD [Analog Devices], AD7885 Datasheet - Page 3

• Manufacturer Part Number: AD7885
• Description: LC2MOS 16-Bit, High Speed Sampling ADCs
• Manufacturer: AD [Analog Devices]

REV. C
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
Model
AD7884AN –40 C to +85 C
AD7884BN –40 C to +85 C
AD7884AP
AD7884BP
AD7885AN –40 C to +85 C
AD7885BN –40 C to +85 C
AD7885AAP –40 C to +85 C
AD7885ABP –40 C to +85 C
NOTES
1
2
Timing specifications in bold print are 100% production tested. All other times are sample tested at +5 C to ensure compliance. All input signals are specified
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
olated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
bus relinquish time of the part and as such is independent of external bus loading capacitances.
Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic
DIP (N) packages.
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).
6
7
2
3
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrap-
1
Linearity
Temperature
Range
–40 C to +85 C
–40 C to +85 C
Limit at +25 C
(All Versions)
50
100
0
60
0
57
5
50
40
10
25
60
60
55
55
ORDERING GUIDE
Error
(% FSR)
0.0075
0.0075
0.0075
0.0075
Limit at T
(A, B Versions)
50
100
0
60
0
57
5
50
40
80
25
60
60
70
70
1, 2
(V
SNR
(dB)
84
84
84
84
84
84
84
84
DD
= +5 V
MIN
, T
Package
Option
N-40A
N-40A
P-44A
P-44A
N-28A
N-28A
P-44A
P-44A
MAX
5%, V
2
Units
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
SS
–3–
= –5 V
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time
5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)
Conditions/Comments
CONVST Pulse Width
CONVST to BUSY Low Delay
CS to RD Setup Time
RD Pulse Width
CS to RD Hold Time
Data Access Time after RD
Bus Relinquish Time after RD
New Data Valid before Rising Edge of BUSY
HBEN to RD Setup Time
HBEN to RD Hold Time
HBEN Low Pulse Duration
HBEN High Pulse Duration
Propagation Delay from HBEN Falling to Data Valid
Propagation Delay from HBEN Rising to Data Valid
TO OUTPUT PIN
100pF
C
L
7
, quoted in the Timing Characteristics is the true
1.6mA
200 A
AD7884/AD7885
I
I
OL
OH
+2.1V