AD7885 AD [Analog Devices], AD7885 Datasheet - Page 8

• Manufacturer Part Number: AD7885
• Description: LC2MOS 16-Bit, High Speed Sampling ADCs
• Manufacturer: AD [Analog Devices]

AD7884/AD7885
The required +3 V reference is derived from the AD780 and
buffered by the high-speed amplifier A3 (AD845, AD817 or
equivalent). A4 is a unity gain inverter which provides the –3 V
negative reference. The gain setting resistors are on-chip and
are factory trimmed to ensure precise tracking of V
6 shows A3 and A4 as AD845s or AD817s. These have the ability
to respond to the rapidly changing reference input impedance.
CIRCUIT DESCRIPTION
Analog Input Section
The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1a goes open circuit to put the SHA into the
hold mode, SW1b is closed. This means that the input resis-
tors, R1 and R2 are always connected to either virtual ground
or true ground.
When the 3 V
put section has a gain of –0.6 and transforms an input signal
of 5 volts to the required 3 volts. When the 5 V
–1 and so the analog input range is now 3 volts. Resistors R4
and R5, at the amplifier output, further condition the 3 volts
signal to be 0 to –3 volts. This is the required input for the 9-bit
A/D converter section.
With SW1a closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the CONVST pulse, SW1a goes open circuit, and capacitor C1
holds the voltage on the output of A1. The sample-and-
hold is now in the hold mode. The aperture delay time for the
sample-and-hold is nominally 50 ns.
3V
5V
5 V
3V
5V
IN
IN
IN
IN
S
IN
S
F
F
Figure 7. AD7884/AD7885 Analog Input Section
F inputs are grounded, the input section has a gain of
R1 3k
R2 5k
IN
SW1b
S and 3 V
SW1a
R3 3k
AMPLIFIER A2
IN
TO RESIDUE
F inputs are tied to 0 V, the in-
A1
C1
R6 2k
R4 4k
V
REF+
IN
REF–
R5 4k
S and
. Figure
TO
9-BIT
ADC
–8–
A/D Converter Section
The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is pre-
sented to the input of the 9-bit ADC. The first phase of
conversion generates the 9 MSBs of the 16-bit result and trans-
fers these to the latch and ALU combination. They are also fed
back to the 9 MSBs of the 16-bit DAC. The 7 LSBs of the
DAC are permanently loaded with 0s. The DAC output is sub-
tracted from the analog input with the result being amplified
and offset in the Residue Amplifier Section. The signal at the
output of A2 is proportional to the error between the first phase
result and the actual analog input signal and is digitized in the
second conversion phase. This second phase begins when the
16-bit DAC and the Residue Error Amplifier have both settled.
First, SW2 is turned off and SW3 is turned on. Then, the SHA
section of the Residue Amplifier goes into hold mode. Next
SW2 is turned off and SW3 is turned on. The 9-bit result is
transferred to the output latch and ALU. An error correction al-
gorithm now compensates for the offset inserted in the Residue
Amplifier Section and errors introduced in the first pass conver-
sion and combines both results to give the 16-bit answer.
FROM INPUT
3V SIGNAL
SHA
2k
R6
Figure 8. A/D Converter Section
V
REF+
R4
RESIDUE AMP
F
4k
4k
+
V
R5
A2
REF+
SHA
ACCURATE
+3V
2k
16-BIT
R7
DAC
0 TO –3V
S
V
REF–
V
–3V
INV
SW3
2k
R8
SW2
V
9
REF–
9-BIT
ADC
9
9
LATCH
ALU
+
REV. C
16