MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 2

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

GENERAL DESCRIPTION
random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the posi-
tive edge of the clock signal, CLK). Each of the x4’s
134,217,728-bit banks is organized as 8,192 rows by 4,096
columns by 4 bits. Each of the x8’s 134,217,728-bit banks
is organized as 8,192 rows by 2,048 columns by 8 bits.
Each of the x16’s 134,217,728-bit banks is organized as
8,192 rows by 1,024 columns by 16 bits.
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-A12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
The 512Mb SDRAM is a high-speed CMOS, dynamic
Read and write accesses to the SDRAM are burst ori-
The SDRAM provides for programmable READ or
2
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
tecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully ran-
dom access. Precharging one bank while accessing one of
the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
auto refresh mode is provided, along with a power-sav-
ing, power-down mode. All inputs and outputs are LVTTL-
compatible.
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle
during a burst access.
The 512Mb SDRAM uses an internal pipelined archi-
The 512Mb SDRAM is designed to operate at 3.3V. An
SDRAMs offer substantial advances in DRAM operat-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16
©2000, Micron Technology, Inc.
SDRAM
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