MT48LC128M4A2TG MICRON [Micron Technology], MT48LC128M4A2TG Datasheet - Page 27

• Manufacturer Part Number: MT48LC128M4A2TG
• Description: SYNCHRONOUS DRAM
• Manufacturer: MICRON [Micron Technology]

TRUTH TABLE 2 – CKE
(Notes: 1-4)
NOTE: 1. CKE
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
CKE
H
H
L
L
n-1
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at
CKE
(provided that
or NOP commands should be issued on any clock edges occurring during the
commands must be provided during
clock edge n + 1.
H
H
L
L
n
n
is the logic state of CKE at clock edge n; CKE
Reading or Writing
CURRENT STATE
n
Clock Suspend
Clock Suspend
All Banks Idle
All Banks Idle
Power-Down
Power-Down
Self Refresh
Self Refresh
is the command registered at clock edge n, and ACTION
t
CKS is met).
See Truth Table 3 (page 28)
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
t
XSR period.
AUTO REFRESH
COMMAND
VALID
n-1
X
X
X
X
27
was the state of CKE at the previous clock edge.
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
is a result of COMMAND
ACTION
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
t
XSR period. A minimum of two NOP
512Mb: x4, x8, x16
n
t
XSR is met. COMMAND INHIBIT
n
.
©2000, Micron Technology, Inc.
SDRAM
ADVANCE
NOTES
6
5
7