CY7C132 CYPRESS [Cypress Semiconductor], CY7C132 Datasheet - Page 6

• Manufacturer Part Number: CY7C132
• Description: 2Kx8 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
12. AC test conditions use V
13. At any given temperature and voltage condition for any given device, t
14. t
15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C142/CY7C146 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
19. 52-pin PLCC and PQFP versions only.
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
DDD
WDD
WINS
EINS
INS
OINR
EINR
INR
WRITE CYCLE
BUSY/INTERRUPT TIMING
INTERRUPT TIMING
I
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
OL
LZCE
/I
OH,
, t
LZWE
and 30-pF load capacitance.
, t
HZOE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
R/W HIGH to Low Z
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
Write Data Valid to Read Data Valid
Write Pulse to Data Delay
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset Time
Address to INTERRUPT Reset Time
[15]
, t
LZOE,
[19]
t
OH
HZCE,
= 1.6V and V
and t
HZWE
Over the Operating Range
[10]
[10]
OL
are tested with C
= 1.4V.
[17]
[16]
[16]
[16]
L
= 5pF as in part (b) of AC Test Loads . Transition is measured ±500 mV from steady-state voltage.
[16]
[16]
[6, 11]
HZCE
35
30
30
25
15
30
6
2
0
0
0
5
0
is less than t
7C132-35
7C136-35
7C142-35
7C146-35
(continued)
Note
Note
LZCE
20
20
20
20
20
35
18
18
25
25
25
25
25
25
and t
HZOE
45
35
35
30
20
35
2
0
0
0
5
0
7C132-45
7C136-45
7C142-45
7C146-45
is less than t
Note
Note
20
25
25
25
25
45
18
18
35
35
35
35
35
35
LZOE
CY7C132/CY7C136
CY7C142/CY7C146
.
55
40
40
30
35
20
2
0
0
0
5
0
7C132-55
7C136-55
7C142-55
7C146-55
Note
Note
25
30
30
30
30
45
18
18
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns