MT4C1M16C3 MICRON [Micron Technology], MT4C1M16C3 Datasheet - Page 3

• Manufacturer Part Number: MT4C1M16C3
• Description: FPM DRAM
• Manufacturer: MICRON [Micron Technology]

GENERAL DESCRIPTION (continued)
in order to retain stored data.
FAST PAGE MODE ACCESS
erations (READ, WRITE or READ-MODIFY-WRITE)
within a row-address-defined (A0-A9) page boundary.
The FAST-PAGE-MODE cycle is always initiated with a
row address strobed in by RAS#, followed by a column
address strobed in by CAS#. Additional columns may
be accessed by providing valid column addresses,
strobing CAS# and holding RAS# LOW, thus executing
faster memory cycles. Returning RAS# HIGH termi-
nates the FAST-PAGE-MODE operation.
memory cycle and decreases chip current to a reduced
standbylevel. The chip is also preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining power
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
The MT4LC1M16C3 must be refreshed periodically
FAST-PAGE-MODE operations allow faster data op-
Returning RAS# and CAS# HIGH terminates a
LOWER BYTE
UPPER BYTE
(DQ8-DQ15)
(DQ0-DQ7)
OF WORD
OF WORD
CASH#
CASL#
RAS#
WE#
STORED
X = NOT EFFECTIVE (DON'T CARE)
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
WORD and BYTE WRITE Example
INPUT
DATA
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
ADDRESS 0
WORD WRITE
INPUT
DATA
1
0
1
0
1
1
1
1
Figure 1
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
3
STORED
DATA
and executing anyRAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that
all 1,024 combinations of RAS# addresses (A0-A9) are
executed at least every 16ms (128ms on the “S” ver-
sion), regardless of sequence. The CBR REFRESH cycle
will also invoke the refresh counter and controller for
row-address control.
BYTE ACCESS CYCLE
by the use of CASL# and CASH#. Enabling CASL# will
select a lower byte access (DQ0-DQ7), while enabling
CASH# will select an upper byte access (DQ0-DQ15).
Enabling both CASL# and CASH# selects a WORD
WRITE cycle.
8 DRAMs that have common input controls, with the
exception of the CAS# inputs. Figure 1 illustrates the
BYTE WRITE and WORD WRITE cycles. Figure 2 illus-
trates BYTE READ and WORD READ cycles.
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
The BYTE WRITEs and BYTE READs are determined
The 1 Meg x 16 DRAM may be viewed as two 1 Meg x
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LOWER BYTE WRITE
INPUT
DATA
ADDRESS 1
1
1
0
1
1
1
1
1
X
X
X
X
X
X
X
X
INPUT
DATA
STORED
DATA
1
0
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1 MEG x 16
FPM DRAM
©2001, Micron Technology, Inc.