CY7C1360B CYPRESS [Cypress Semiconductor], CY7C1360B Datasheet - Page 10

• Manufacturer Part Number: CY7C1360B
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05291 Rev. *C
CY7C1362B–Pin Definitions
ADSP
ADSC
ZZ
DQs,
DQPs
V
V
V
DD
SS
SSQ
Name
5,10,21,26,
72,73,8,9,
58,59,62,
63,68,69,
12,13,18,
19,22,23,
15,41,65,
17,40,67,
55,60,71,
Enable
3-Chip
TQFP
74,24
84
85
64
91
90
76
5,10,21,26,
72,73,8,9,
58,59,62,
63,68,69,
12,13,18,
19,22,23,
15,41,65,
17,40,67,
55,60,71,
Enable
2-Chip
TQFP
74,24
84
85
64
91
90
76
E5,E3,F3,
F6,H6,L6,
K3,K5,L3,
C4,J2,J4,
(continued)
M3,M5,
G7,E7,
N6,D1,
G2,K2,
M2,D6,
D3,D5,
H3,H5,
N3,N5,
P7,K7,
N1,E2,
F5,G5,
H1,L1,
P3,P5
J6,R4
BGA
A4
P4
T7
P2
-
F11,G11,J1,
D5,D6,D7,E
K1,L1,M1,D
D4,D8,E4,E
H5,H6,H7,J
G2,C11,N1
M5,M6,M7,
G5,G6,G7,
G4,G8,H4,
H2,C4,C5,
C6,C7,C8,
L8,M4,M8
K5,K6,K7,
K4,K8,L4,
F5,F6,F7,
L10,M10,
H8,J4,J8,
L5,L6,L7,
D11,E11,
J10,K10,
2,E2,F2,
5,E6,E7,
8,F4,F8,
5,J6,J7,
N4,N8
fBGA
H11
B9
A8
-
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
I/O Ground
Ground
Input-
Input-
Input-
I/O-
I/O
Address Strobe from Processor, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
nized. ASDP is ignored when CE
HIGH.
Address Strobe from Controller, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A
also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recog-
nized.
ZZ “Sleep” Input, active HIGH. When asserted
HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the
data contained in the memory location specified by
the addresses presented during the previous clock
rise of the a Read cycle. The direction of the pins
is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and
DQP
Ground for the core of the device.
Ground for the I/O circuitry.
X
are placed in a three-state condition.
Description
CY7C1360B
CY7C1362B
1
is deasserted
Page 10 of 34
1
1
, A
, A
0
0
are
are