CY7C1360B CYPRESS [Cypress Semiconductor], CY7C1360B Datasheet - Page 7

• Manufacturer Part Number: CY7C1360B
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05291 Rev. *C
CY7C1360B–Pin Definitions
ADSP
ADSC
ZZ
DQs,
DQPs
V
V
DD
SS
Name
8,9,12,13,1
79,2,3,6,7,
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
23,24,25,
28,29,51,
15,41,65,
17,40,67,
8,19,22,
Enable
80,1,30
3-Chip
TQFP
84
85
64
91
90
8,9,12,13,1
79,2,3,6,7,
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
23,24,25,
28,29,51,
15,41,65,
17,40,67,
8,19,22,
80,1,30
Enable
2-Chip
TQFP
84
85
64
91
90
(continued)
J2,C4,J4,
M6,N6,
M2,N2,
N7,P7,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
G2,H2,
N1,P1,
P6,D6,
D3,E3,
K3,M3,
N3,P3,
D5,E5,
K5,M5,
E6,F6,
E2,F2,
F3,H3,
F5,H5,
K6,L6,
K7,L7,
K1,L1,
K2,L2,
D2,P2
N5,P5
R4,J6
BGA
A4
B4
T7
H5,H6,H7,J
C11,C1,N1
M5,M6,M7,
G4,G8,H4,
G6,G7,H2,
G1,D2,E2,
C4,C5,C6,
C7,C8,D5,
D1,E1,F1,
K1,L1,M1,
D4,D8,E4,
D6,D7,E5,
F6,F7,G5,
K5,K6,K7,
F2,G2,J1,
E8,F4,F8,
K4,K8,L4,
L8,M4,M8
E6,E7,F5,
L10,M10,
D10,E10,
F10,G10,
J2,K2,L2,
H8,J4,J8,
L5,L6,L7,
M11,L11,
D11,E11,
F11,G11,
J10,K10,
K11,J11,
M2,N11,
5,J6,J7,
N4,N8
fBGA
H11
B9
A8
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
Asynchro-
Ground
Input-
Input-
Input-
nous
I/O-
I/O
Address Strobe from Processor, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A
also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are
captured in the address registers. A
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ “Sleep” Input, active HIGH. When asserted
HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the
addresses presented during the previous clock rise
of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and
DQP
Ground for the core of the device.
X
are placed in a three-state condition.
Description
1
is deasserted HIGH.
CY7C1360B
CY7C1362B
1
, A
Page 7 of 34
0
1
, A
are also
0
are